 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| stpc ? ELITE x86 core general purpose pc compatible system - on - chip release 1.3 - january 29, 2002 1/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. logic diagram n powerful x86 processor n 64-bit sdram controller at 100mhz n integrated pci north / south bridge controller n isa master / slave / dma n 16-bit local bus interface for low cost and embedded applications n eide controller n integrated peripheral controller - dma controller - interrupt controller - timer / counters n power management unit n i2c interface n 16 enhanced general purpose i/os. n jtag ieee1149.1 n programmable output clock up to 135mhz n commercial and industrial tem- perature ranges description the stpc ELITE integrates a fully static x86 processor up to 133 mhz, fully compatible with standard x86 processors, and combines it with powerful chipset to provide a general purpose pc compatible subsystem on a single device. the device is packaged in a 388 ball grid array (pbga). the stpc ELITE has a low voltage operation with v core = 2.5v and has 5v tolerant i/os (3.3v output levels). pbga388 s t p c e l i t e x86 core host i/f sdram control pci i/f pci isa i/f eide ctrl pci i/f isa bus eide l.b. i/f local bus ipc jtag pmu
2/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. n x86 processor core n fully static 32-bit 5-stage pipeline, x86 processor fully pc compatible. n can access up to 4gb of external memory. n 8kbyte unified instruction and data cache with write back and write through capability. n parallel processing integral floating point unit, with automatic power down. n clock core speeds up to of 100 mhz in x1 clock mode and 133mhz in x2 mode. n fully static design for dynamic clock control. n low power and system management modes. n sdram controller n 64-bit data bus. n up to 100mhz sdram clock speed. n supports up to 128 mb system memory. n supports 16-, 64- and 128-mbit memories. n supports up to 4 memory banks. n supports buffered, non buffered, registered dimms n 4-line write buffers for cpu to dram and pci to dram cycles. n 4-line read prefetch buffers for pci masters. n programmable latency n programmable timing for dram parameters. n supports -8, -10, -12, -13, -15 memory parts n supports memory hole between 1mb and 8mb for pci/isa busses. n pci controller n compliant with pci 2.1 specification. n integrated pci arbitration interface. up to 3 masters can connect directly. external logic allows for greater than 3 masters. n translation of pci cycles to isa bus. n translation of isa master initiated cycle to pci. n support for burst read/write from pci master. n 0.25x, 0.33x and 0.5x host clock pci clock. n isa master/slave n generates the isa clock from either 14.318mhz oscillator clock or pci clock n supports programmable extra wait state for isa cycles n supports i/o recovery time for back to back i/o cycles. n fast gate a20 and fast reset. n supports the single rom that c, d, or e. blocks shares with f block bios rom. n supports flash rom. n supports isa hidden refresh. n buffered dma & isa master cycles to reduce bandwidth utilization of the pci and host bus. nsp compliant. n 16-bit i/o decoding. n local bus interface n multiplexed with isa/dma/timer functions. n high speed, low latency bus. n supports 32-bit flash burst. n 16-bit data bus with word steering capability. n separate memory and i/o address spaces. n programmable timing (host clock granularity) n supports 2 cachable banks of 16mb flash devices with boot block shadowed to 0x000f0000. n 2 programmable flash/eprom chip select. n 4 programmable i/o chip select. n 2-level hardware key protection for flash boot block protection. n 24 bit address bus. n eide controller n compatible with eide (ata-2). n backward compatibility with ide (ata-1). n supports up to 4 ide devices n supports pio and bus master ide n concurrent channel operation (pio & dma modes) - 4 x 32-bit buffer fifo per channel n support for 11.1/16.6 mb/s, i/o channel ready pio data transfers. n bus master with scatter/gather capability. n multi-word dma support for fast ide drives. n individual drive timing for all four ide devices. n supports both legacy & native ide modes. n supports hard drives larger than 528mb. n support for cd-rom and tape peripherals. n integrated peripheral controller n 2x8237/at compatible 7-channel dma controller. n 2x8259/at compatible interrupt controller. 16 interrupt inputs - isa and pci. n three 8254 compatible timer/counters. n co-processor error support logic. n supports external rtc. n power management n four power saving modes: on, doze, standby, suspend. release 1.3 - january 29, 2002 3/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. n programmable system activity detector n supports smm. n supports stopclk. n supports io trap & restart. n independent peripheral time-out timer to monitor hard disk, serial & parallel ports. n supports rtc, interrupts and dmas wake-up n gpios n 16 enhanced general purpose io. n jtag function n programmable gp-clock n this clock is programmable to frequencies up to 135 mhz. 4/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. general description release 1.3 - january 29, 2002 5/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 1. general description at the heart of the stpc ELITE is an advanced processor block that includes a powerful x86 processor core along with a 64-bit sdram controller, a high speed pci local-bus controller and industry standard pc chip set functions (interrupt controller, dma controller, interval timer and isa bus) and eide controller. the processor bus runs at the speed of the processor (x1 mode) or half the speed (x2 mode). the stmicroelectronics x86 processor core is embedded with standard and application specific peripheral modules on the same silicon die. the core has all the functionality of the st standard x86 processor products, including the low power system management mode (smm). system management mode (smm) provides an additional interrupt and address space that can be used for system power management or software transparent emulation of peripherals. while running in isolated smm address space, the smm interrupt routine can execute without interfering with the operating system or application programs. the standard pc chipset functions (dma, interrupt controller, timers, power management logic) are integrated with the x86 processor core. the pci bus is the main data communication link to the stpc ELITE chip. the stpc ELITE translates appropriate host bus i/o and memory cycles onto the pci bus. it also supports generation of configuration cycles on the pci bus. the stpc ELITE, as a pci bus agent (host bridge class), fully complies with pci specification 2.1. the chip-set also implements the pci mandatory header registers in type 0 pci configuration space for easy porting of pci aware system bios. the device contains a pci arbitration function for three external pci devices. the stpc ELITE integrates an isa bus controller. peripheral modules such as parallel and serial communications ports, keyboard controllers and additional isa devices can be accessed by the stpc ELITE chip set through this bus. an industry standard eide (ata 2) controller is built in to the stpc ELITE and connected internally via the pci bus. 1.1. memory controller the stpc handles the memory data (data) bus directly, controlling from 8 to 128 mbytes. the sdram controller supports accesses to the memory banks to/from the cpu (via the host). parity is not supported. the sdram controller only supports 64 bit wide memory banks. four memory banks (if dimms are used; single sided or two double-sided dimms) are supported in the following configurations (see table 1-1 ) the sdram controller supports buffered or unbuffered sdram but not edo or fpm modes. sdrams must support full page mode type access. the stpc memory controller provides various programmable sdram parameters to allow the sdram interface to be optimized for different processor bus speeds sdram speed grades and cas latency. 1.2. power management the stpc ELITE core is compliant with the advanced power management (apm) specification to provide a standard method by which the bios can control the power used by personal computers. the power management unit (pmu) module controls the power consumption, providing a comprehensive set of features that controls the power usage and supports compliance with the united states environmental protection agency's energy star computer program. the pmu provides the following hardware structures to assist the software in managing the system power consumption: - system activity detection. table 1-1. memory configurations memory bank size number organisa tion device size 1mx64 4 1mx16 16mbits 2mx64 8 2mx8 4mx64 16 4mx4 4mx64 4 2mx16x2 64mbits 8mx64 8 4mx8x2 16mx64 16 8mx4x2 4mx64 4 1mx16x4 8mx64 8 2mx8x4 32mx64 16 4mx4x4 16mx64 8 2mx16x2 128mbits 32mx64 16 4mx8x4 general description 6/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. - 3 power-down timers detecting system inactivity: - doze timer (short durations). - stand-by timer (medium durations). - suspend timer (long durations). - house-keeping activity detection. - house-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state. - peripheral activity detection. - peripheral timer detecting peripheral inactivity - susp# modulation to adjust the system performance in various power down states of the system including full power-on state. - power control outputs to disable power from different planes of the board. lack of system activity for progressively longer periods of time is detected by the three power down timers. these timers can generate smi interrupts to cpu so that the smm software can put the system in decreasing states of power consumption. alternatively, system activity in a power down state can generate an smi interrupt to allow the software to bring the system back up to full power-on state. the chip-set supports up to three power down states described above; these correspond to decreasing levels of power savings. power down puts the stpc ELITE into suspend mode. the processor completes execution of the current instruction, any pending decoded instructions and associated bus cycles. during the suspend mode, internal clocks are stopped. removing power-down, the processor resumes instruction fetching and begins execution in the instruction stream at the point it had stopped. because of the static nature of the core, no internal data is lost. 1.3. jtag jtag stands for joint test action group and is the popular name for ieee std. 1149.1, standard test access port and boundary-scan architec-ture. this built-in circuitry is used to assist in the test, maintenance and support of functional circuit blocks. the circuitry includes a standard interface through which instructions and test data are communicated. a set of test features is defined, including a boundary-scan register so that a component is able to respond to a minimum set of test instructions. general description release 1.3 - january 29, 2002 7/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. figure 1-1. functional description. pci north bridge host i/f x86 core sdram controller isa m/s eide pci south bridge isa bus ipc 82c206 eide gpio x16 local bus i/f jtag local bus gpclk general description 8/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 1.4. clock tree the stpc ELITE integrates many features and generates all its clocks from a single 14mhz oscillator. this results in multiple clock domains as described in figure 1-2 . the speed of the plls is either fixed (devclk), either programmable by strap option (hclk) either programmable by software (gpclk, mclk). when in synchronized mode, mclk speed is fixed to hclko speed and hclki is generated from mclki. figure 1-2. stpc ELITE clock architecture ipc sdram controller north bridge 14.31818 mhz xtalo xtali osc14m isaclk 1/4 gpclk gpclk pll (14mhz) 1/2 hclk pll pciclki pciclko south bridge 1/2 1/3 hclk mclk pll mclki mclko cpu x1 x2 local bus host isa hclki hclko general description release 1.3 - january 29, 2002 9/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. figure 1-3. typical isa-based application. stpc ELITE isa pci 4x 16-bit sdrams super i/o 2x eide flash keyboard / mouse serial ports parallel port floppy irq dma.req dma.ack dmux dmux mux mux rtc gpios gpclk general description 10/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. pin description release 1.3 - january 29, 2002 11/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 2. pin description 2.1. introduction the stpc ELITE integrates most of the functionalities of the pc architecture. as a result, many of the traditional interconnections between the host pc microprocessor and the peripheral devices are totally internal to the stpc ELITE. this offers improved performance due to the tight coupling of the processor core and these peripherals. as a result many of the external pin connections are made directly to the on-chip peripheral functions. figure 2-1 shows the stpc ELITE external interfaces. it defines the main buses and their function. table 2-1 describes the physical implementation listing signals type and their functionality. table 2-2 provides a full pin listing and description of pins. table 2-7 provides a full listing of pin locations of the stpc ELITE package by physical connection. note: several interface pins are multiplexed with other functions, refer to table 2-4 and table 2-5 for further details table 2-1. signal description group name qty basic clocks reset & xtal 6 memory interface 96 pci interface 56 isa 79 90 ide 34 local bus 50 grounds 69 v dd 22 miscellaneous 8 gpio 16 unconnected 25 total pin count 388 figure 2-1. stpc ELITE external interfaces south north pci x86 sdram i/f sys isa/ide/lb 96 56 6 90 stpc ELITE pin description 12/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. table 2-2. definition of signal pins signal name dir buffer type 2 description qty basic clocks and resets sysrseti# i schmitt_ft system power good input 1 sysrsto# o bd8strp_ft system reset output 1 xtali i ana 14.3 mhz crystal input - external oscillator input 1 xtalo i/o osci13b 14.3 mhz crystal output 1 hclk i/o bd4strp_ft host clock (test) 1 gp_clk o bt8trp_tc general purpose clock 1 v dd _xxx_pll 1 power supply for pll clocks memory interface mclki i tlcht_tc memory clock input 1 mclko o bt8trp_tc memory clock output 1 cs#[1:0] o bd8strp_tc dimm chip select 2 cs#[3]/ma[13]/ba[1] o bd16staruqp_tc dimm chip select/ memory address/ bank address 1 cs#[2]/ma[12] o bd16staruqp_tc dimm chip select/ bank address 1 ma[10:0] o bd16staruqp_tc memory row & column address 12 md[48:10], [7:2] i/o bd8trp_tc memory data 45 md[63:49], [9:8], [1:0] i/o bd8strup_ft memory data 19 ras#[1:0] o bd16staruqp_tc row address strobe 2 cas#[1:0] o bd16staruqp_tc column address strobe 2 mwe# o bd16staruqp_tc write enable 1 dqm[7:0] o bd8strp_tc data input/output mask 8 pci interface pci_clki i tlcht_ft 33 mhz pci input clock 1 pci_clko o bt8trp_tc 33 mhz pci output clock (from internal pll) 1 ad[31:0] i/o bd8pciarp_ft pci address / data 32 cbe[3:0] i/o bd8pciarp_ft bus commands / byte enables 4 frame# i/o bd8pciarp_ft cycle frame 1 irdy# i/o bd8pciarp_ft initiator ready 1 trdy# i/o bd8pciarp_ft target ready 1 lock# i tlcht_ft pci lock 1 devsel# i/o bd8pciarp_ft device select 1 stop# i/o bd8pciarp_ft stop transaction 1 par i/o bd8pciarp_ft parity signal transactions 1 serr# o bd8pciarp_ft system error 1 pci_req#[2:0] i bd8pciarp_ft pci request 3 pci_gnt#[2:0] o bd8pciarp_ft pci grant 3 pci_int[3:0] i bd4strup_ft pci interrupt request 4 isa control note 1 : these pins must be connected to the 2.5 v power supply. they must not be connected to the 3.3v supply. note 2 : see table 2-3 for buffer type descriptions. pin description release 1.3 - january 29, 2002 13/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. isa_clk o bt8trp_tc isa clock output - multiplexer select line for ipc 1 isa_clk2x o bt8trp_tc isa clock x2 output - multiplexer select line for ipc 1 osc14m o bd8strp_ft buffered 14mhz clock 1 la[23:17] o bd8strup_ft unlatched address 7 sa[19:0] i/o bd8strup_ft latched address 20 sd[15:0] i/o bd8strp_ft data bus 16 ale o bd4strp_ft address latch enable 1 memr#, memw# i/o bd8strup_ft memory read and memory write 2 smemr#, smemw# o bd8strup_ft system memory read and memory write 2 ior#, iow# i/o bd8strup_ft i/o read and write 2 mcs16#, iocs16# i bd4strup_ft memory/io chip select16 2 bhe# o bd8strup_ft system bus high enable 1 zws# i bd4strp_ft zero wait state 1 ref# o bd8strp_ft refresh cycle. 1 master# i bd4strup_ft add on card owns bus 1 aen o bd8strup_ft address enable 1 iochck# i bd4strup_ft i/o channel check. 1 iochrdy i/o bd8strup_ft i/o channel ready (isa) - busy/ready (ide) 1 isaoe# o bd4strp_ft isa/ide selection 1 gpiocs# i/o bd4strp_ft general purpose chip select 1 irq_mux[3:0] i bd4strp_ft time-multiplexed interrupt request 4 dreq_mux[1:0] i bd4strp_ft time-multiplexed dma request 2 dack_enc[2:0] o bd4strp_ft encoded dma acknowledge 3 tc o bd4strp_ft isa terminal count 1 rtcas o bd4strp_ft real time clock address strobe 1 rmrtccs# i/o bd4strp_ft rom/rtc chip select 1 kbcs# i/o bd4strp_ft keyboard chip select 1 rtcrw# i/o bd4strp_ft rtc read/write 1 rtcds# i/o bd4strp_ft rtc data strobe 1 local bus pa[23:20], [15], [8], [3:0] o bd4strp_ft address bus 10 pa[19:16], [14:12],[7:4] o bd8strup_ft address bus 11 pa[11] o bd8strp_ft address bus 1 pa[10:9] o bd4strup_ft address bus 2 pd[15:0] i/o bd8strp_ft data bus 16 prd1#,prd0# o bd4strup_ft peripheral read control 2 pwr1# o bd8strup_ft peripheral write control 1 pwr0# o bd4strup_ft peripheral write control 1 prdy i bd8strup_ft data ready 1 fcs1#, fcs0# o bd4strp_ft flash chip select 2 iocs#[3] o bd4strp_ft i/o chip select 1 iocs#[2:0] o bd8strup_ft i/o chip select 3 table 2-2. definition of signal pins signal name dir buffer type 2 description qty note 1 : these pins must be connected to the 2.5 v power supply. they must not be connected to the 3.3v supply. note 2 : see table 2-3 for buffer type descriptions. pin description 14/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. ide control da[2:0] o bd8strup_ft address bus 3 dd[15:12] i/o bd4strp_ft data bus 4 dd[11:0] i/o bd8strup_ft data bus 12 pcs3#,pcs1#,scs3#,scs1# o bd8strup_ft primary & secondary chip selects 4 diordy o bd8strup_ft data i/o ready 1 pirq, sirq i bd4strp_ft primary & secondary interrupt request 2 pdrq, sdrq i bd4strp_ft primary & secondary dma request 2 pdack#, sdack# o bd8strp_ft primary & secondary dma acknowledge 2 pdior#, sdior# o bd8strup_ft primary & secondary i/o channel read 2 pdiow#, sdiow# o bd8strp_ft primary & secondary i/o channel write 2 miscellaneous gpio[15:0] i/o bd4strp_ft general purpose i/os 16 spkrd o bd4strp_ft speaker device output 1 scl i/o bd4strup_ft i2c interface - clock / can be used for vga ddc[1] signal 1 sda i/o bd4strup_ft i2c interface - data / can be used for vga ddc[0] signal 1 scan_enable i tlchtd_tc reserved (test pin) 1 tclk i bd4strp_ft test clock 1 tdi i bd4strp_ft test data input 1 tms i bd4strp_ft test mode input 1 tdo o bd4strp_ft test data output 1 table 2-2. definition of signal pins signal name dir buffer type 2 description qty note 1 : these pins must be connected to the 2.5 v power supply. they must not be connected to the 3.3v supply. note 2 : see table 2-3 for buffer type descriptions. pin description release 1.3 - january 29, 2002 15/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. table 2-3. buffer type descriptions buffer description ana analog pad buffer osci13b oscillator, 13 mhz, hcmos bt8trp_tc lvttl bi-directional, 8 ma drive capability, schmitt trigger bd4strp_ft lvttl bi-directional, 4 ma drive capability, schmitt trigger, 5v tolerant bd4strup_ft lvttl bi-directional, 4 ma drive capability, schmitt trigger, pull-up, 5v tolerant bd8strp_ft lvttl bi-directional, 8 ma drive capability, schmitt trigger, 5v tolerant bd8strup_ft lvttl bi-directional, 8 ma drive capability, schmitt trigger, pull-up, 5v tolerant bd8strp_tc lvttl bi-directional, 8 ma drive capability, schmitt trigger bd8trp_tc lvttl bi-directional, 8 ma drive capability, schmitt trigger bd8pciarp_ft lvttl bi-directional, 8 ma drive capability, pci compatible, 5v tolerant bd16staruqp_tc lvttl bi-directional, 16 ma drive capability, schmitt trigger schmitt_ft lvttl input, schmitt trigger, 5v tolerant tlcht_ft lvttl input, 5v tolerant tlcht_tc lvttl input tlchtd_tc lvttl input, pull-down pin description 16/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 2.2. signal descriptions 2.2.1. basic clocks and resets sysrsti# system reset/power good. this input is low when the reset switch is depressed. otherwise, it reflects the power supplys power good signal. this input is asynchronous to all clocks, and acts as a negative active reset. the reset circuit initiates a hard reset on the rising edge of this signal. sysrsto# reset output to system. this is the system reset signal and is used to reset the rest of the components (not on host bus) in the system. the isa bus reset is an externally inverted buffered version of this output and the pci bus reset is an externally buffered version of this output. xtali 14.3 mhz crystal input xtalo 14.3 mhz crystal output. these pins are provided for the connection of an external 14.318 mhz crystal to provide the reference clock for the internal frequency synthesizer, from which all other clock signals are generated. the 14.318 mhz series-cut fundamental (not overtone) mode quartz crystal must have an equivalent series resistance (esr, sometimes referred to as rm) of less then 50 ohms (typically 8 ohms) and a shunt capacitance (co) of less than 7 pf. balance capacitors of 16 pf should also be added, one connected to each pin. in the event of an external oscillator providing the master clock signal to the stpc ELITE device, the ttl signal should be connected to xtali. hclk host clock. this clock supplies the cpu and the host related blocks. this clock can e doubled inside the cpu and is intended to operate in the range of 25 to 100 mhz. this clock in generated internally from a pll but can be driven directly from the external system. gp_clk general purpose clock. this clock is programmable and its frequency can be as high as 135 mhz. 2.2.2. memory interface mclki memory clock input. this clock is driving the sdram controller. this input should be a buffered version of the mclko when more than 4 sdram chips are used. go to section 6.3 for more details. mclko memory clock output. this clock is driving the sdram devices and is generated from an internal pll. the default value is 66 mhz. cs#[2]/ma[11] chip select/ bank address this pin is cs#[2] in the case when 16 mbit devices are used. for all other densities, it becomes ma[11]. cs#[3]/ma[12]/ba[1] chip select/ memory address/ bank address this pin is cs#[3] in the case when 16mbit devices are used. for all other densities, it becomes ma[12] when 2 internal banks devices are used and ba[1] when 4 internal bank devices are used. ma[10:0] memory address. multiplexed row and column address lines. ba[0] memory bank address. cs#[1:0] chip select. these signals are used to disable or enable device operation by masking or enabling all sdram inputs except mclk, cke, and dqm. md[63:0] memory data. this is the 64-bit memory data bus. md[40-0] are read by the device strap option registers during rising edge of sysrsti#. ras#[1:0] row address strobe. there are two active-low row address strobe output signals. the ras# signals drive the memory devices directly without any external buffering. cas#[1:0] column address strobe. there are two active-low column address strobe output signals. the cas# signals drive the memory devices directly without any external buffering. mwe# write enable. write enable specifies whether the memory access is a read (mwe# = h) or a write (mwe# = l). dqm#[7:0] data mask. makes data output hi-z after the clock and masks the sdram outputs. blocks sdram data input when dqm active. 2.2.3. pci interface pci_clki 33 mhz pci input clock. this signal is the pci bus clock input and should be driven from the pci_clko pin. pci_clko 33 mhz pci output clock. this is the master pci bus clock output. ad[31:0] pci address/data. this is the 32-bit multiplexed address and data bus of the pci. this bus is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. cbe#[3:0] bus commands/byte enables. these are the multiplexed command and byte enable signals of the pci bus. during the address phase they define the command and during the data pin description release 1.3 - january 29, 2002 17/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. phase they carry the byte enable information. these pins are inputs when a pci master other than the stpc ELITE owns the bus and outputs when the stpc ELITE owns the bus. frame# cycle frame. this is the frame signal of the pci bus. it is an input when a pci master owns the bus and is an output when stpc ELITE owns the pci bus. irdy# initiator ready. this is the initiator ready signal of the pci bus. it is used as an output when the stpc ELITE initiates a bus cycle on the pci bus. it is used as an input during the pci cycles targeted to the stpc ELITE to determine when the current pci master is ready to complete the current transaction. trdy# target ready. this is the target ready signal of the pci bus. it is driven as an output when the stpc ELITE is the target of the current bus transaction. it is used as an input when stpc ELITE initiates a cycle on the pci bus. lock# pci lock. this is the lock signal of the pci bus and is used to implement the exclusive bus operations when acting as a pci target agent. devsel# i/o device select. this signal is used as an input when the stpc ELITE initiates a bus cycle on the pci bus to determine if a pci slave device has decoded itself to be the target of the current transaction. it is asserted as an output either when the stpc ELITE is the target of the current pci transaction or when no other device asserts devsel# prior to the subtractive decode phase of the current pci transaction. stop# stop transaction. stop is used to implement the disconnect, retry and abort protocol of the pci bus. it is used as an input for the bus cycles initiated by the stpc ELITE and is used as an output when a pci master cycle is targeted to the stpc ELITE. par parity signal transactions. this is the parity signal of the pci bus. this signal is used to guarantee even parity across ad[31:0], cbe#[3:0], and par. this signal is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. (its assertion is identical to that of the ad bus delayed by one pci clock cycle) serr# system error. this is the system error signal of the pci bus. it may, if enabled, be asserted for one pci clock cycle if target aborts a stpc ELITE initiated pci transaction. its assertion by either the stpc ELITE or by another pci bus agent will trigger the assertion of nmi to the host cpu. this is an open drain output. pci_req#[2:0] pci request. this pin are the three external pci master request pins. they indicates to the pci arbiter that the external agents desire use of the bus. pci_gnt#[2:0] pci grant. these pins indicate that the pci bus has been granted to the master requesting it on its pcireq#. pci_int[3:0] pci interrupt request. these are the pci bus interrupt signals. 2.2.4. isa interface isa_clk, isa_clkx2 isa clock x1, x2. these pins generate the clock signal for the isa bus and a doubled clock signal. they are also used as the multiplexer control lines for the interrupt controller interrupt input lines. isa_clk is generated from either pciclk/4 or osc14m/ 2. osc14m isa bus synchronisation clock output. this is the buffered 14.318 mhz clock for the isa bus. la[23:17] unlatched address. when the isa bus is active, these pins are isa bus unlatched address for 16-bit devices. when isa bus is accessed by any cycle initiated from pci bus, these pins are in output mode. when an isa bus master owns the bus, these pins are in input mode. sa[19:0] isa address bus. system address bus of isa on 8-bit slot. these pins are used as an input when an isa bus master owns the bus and are outputs at all other times. sd[15:0] i/o data bus. these pins are the external databus to the isa bus. ale address latch enable. this is the address latch enable output of the isa bus and is asserted by the stpc ELITE to indicate that la23-17, sa19- 0, aen and sbhe# signals are valid. the ale is driven high during refresh, dma master or an isa master cycles by the stpc ELITE. ale is driven low after reset. memr# memory read. this is the memory read command signal of the isa bus. it is used as an input when an isa master owns the bus and is an output at all other times. the memr# signal is active during refresh. memw# memory write. this is the memory write command signal of the isa bus. it is used as an input when an isa master owns the bus and is an output at all other times. smemr# system memory read. the stpc ELITE generates smemr# signal of the isa bus only pin description 18/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. when the address is below one megabyte or the cycle is a refresh cycle. smemw# system memory write. the stpc ELITE generates smemw# signal of the isa bus only when the address is below one megabyte. ior# i/o read. this is the io read command signal of the isa bus. it is an input when an isa master owns the bus and is an output at all other times. iow# i/o write. this is the io write command signal of the isa bus. it is an input when an isa master owns the bus and is an output at all other times. mcs16# memory chip select16. this is the decode of la23-17 address pins of the isa address bus without any qualification of the command signal lines. mcs16# is always an input. the stpc ELITE ignores this signal during io and refresh cycles. iocs16# io chip select16. this signal is the decode of sa15-0 address pins of the isa address bus without any qualification of the command signals. the stpc ELITE does not drive iocs16# (similar to pc-at design). an isa master access to an internal register of the stpc ELITE is executed as an extended 8-bit io cycle. bhe# system bus high enable. this signal, when asserted, indicates that a data byte is being transferred on sd15-8 lines. it is used as an input when an isa master owns the bus and is an output at all other times. zws# zero wait state. this signal, when assert- ed by addressed device, indicates that current cy- cle can be shortened. ref# refresh cycle. this is the refresh command signal of the isa bus. it is driven as an output when the stpc ELITE performs a refresh cycle on the isa bus. it is used as an input when an isa master owns the bus and is used to trigger a refresh cycle. the stpc ELITE performs a pseudo hidden refresh. it requests the host bus for two host clocks to drive the refresh address and capture it in external buffers. the host bus is then relinquished while the refresh cycle continues on the isa bus. master# add on card owns bus. this signal is active when an isa device has been granted bus ownership. aen address enable. address enable is enabled when the dma controller is the bus owner to indicate that a dma transfer will occur. the enabling of the signal indicates to io devices to ignore the ior#/iow# signal during dma transfers. iochck# io channel check. io channel check is enabled by any isa device to signal an error condition that can not be corrected. nmi signal becomes active upon seeing iochck# active if the corresponding bit in port b is enabled. iochrdy channel ready. iochrdy is the io channel ready signal of the isa bus and is driven as an output in response to an isa master cycle targeted to the host bus or an internal register of the stpc ELITE. the stpc ELITE monitors this signal as an input when performing an isa cycle on behalf of the host cpu, dma master or refresh. isa masters which do not monitor iochrdy are not guaranteed to work with the stpc ELITE since the access to the system memory can be considerably delayed due uma architecture. isaoe# bidirectional oe control. this signal controls the oe signal of the external transceiver that connects the ide dd bus and isa sa bus. gpiocs# i/o general purpose chip select. this output signal is used by the external latch on isa bus to latch the data on the sd[7:0] bus. the latch can be use by pmu unit to control the external peripheral devices or any other desired function. irq_mux[3:0] multiplexed interrupt request. these are the isa bus interrupt signals. they have to be encoded before connection to the stpc ELITE using isaclk and isaclkx2 as the input selection strobes. note that irq8b, which by convention is connected to the rtc, is inverted before being sent to the interrupt controller, so that it may be connected directly to the irq pin of the rtc. dreq_mux[1:0] isa bus multiplexed dma request. these are the isa bus dma request signals. they are to be encoded before connection to the stpc ELITE using isaclk and isaclkx2 as the input selection strobes. dack_enc[2:0] dma acknowledge. these are the isa bus dma acknowledge signals. they are encoded by the stpc ELITE before output and should be decoded externally using isaclk and isaclkx2 as the control strobes. tc isa terminal count. this is the terminal count output of the dma controller and is connected to the tc line of the isa bus. it is asserted during the last dma transfer, when the byte count expires. 2.2.5. x-bus interface pins rtcas real time clock address strobe. this signal is asserted for any i/o write to port 70h. pin description release 1.3 - january 29, 2002 19/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. rmrtccs# rom/real time clock chip select. this signal is asserted if a rom access is decoded during a memory cycle. it should be combined with memr# or memw# signals to properly access the rom. during a io cycle, this signal is asserted if access to the real time clock (rtc) is decoded. it should be combined with ior or iow# signals to properly access the real time clock. kbcs# keyboard chip select. this signal is asserted if a keyboard access is decoded during a i/o cycle. rtcrw# real time clock rw . this pin is a multi- function pin. when isaoe# is active, this signal is used as rtcrw#. this signal is asserted for any i/o write to port 71h. rtcds# real time clock ds . this pin is a multi- function pin. when isaoe# is active, this signal is used as rtcds# this signal is asserted for any i/ o read to port 71h. its polarity complies with the ds pin of the mt48t86 rtc device when configured with intel timings. note: rmrtccs#, kbcs#, rtcrw# and rtcds# signals must be ored externally with isaoe# and then connected to the external device. an ls244 or equivalent function can be used if oe# is connected to isaoe# and the output is provided with a weak pull-up resistor as shown in design guidelines chapter. 2.2.6. local bus pa[23:0] address bus output. pd[15:0] data bus. this is the 16-bit data bus. d[7:0] is the lsb and pd[15:8] is the msb. prd#[1:0] read control output. prd0# is used to read the lsb and prd1# to read the msb. pwr#[1:0] write control output. pwr0# is used to write the lsb and pwr1# to write the msb. prdy data ready input. this signal is used to create wait states on the bus. when high, it completes the current cycle. fcs#[1:0] flash chip select output. these are the programmable chip select signals for up to 2 banks of flash memory. iocs#[3:0] i/o chip select output. these are the programmable chip select signals for up to 4 external i/o devices. 2.2.7. ide interface da[2:0] address. these signals are connected to da[2:0] of ide devices directly or through a buffer. if the toggling of signals are to be masked during isa bus cycles, they can be externally ored with isaoe# before being connected to the ide devices. dd[15:0] databus. when the ide bus is active, they serve as ide signals dd[11:0]. ide devices are connected to sa[19:8] directly and isa bus is connected to these pins through two ls245 transceivers as described in design guidelines chapter. pcs1#, pcs3# primary chip select. these signals are used as the active high primary master & slave ide chip select signals. these signals must be externally anded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. scs1#, scs3# secondary chip select. these signals are used as the active high secondary master & slave ide chip select signals. these signals must be externally anded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. diordy busy/ready. this pin serves as ide signal diordy. pirq primary interrupt request. sirq secondary interrupt request. interrupt request from ide channels. pdrq primary dma request. sdrq secondary dma request. dma request from ide channels. pdack# primary dma acknowledge. sdack# secondary dma acknowledge. dma acknowledge to ide channels. pdior#, pdiow# primary i/o read & write. sdior#, sdiow# secondary i/o read & write . primary & secondary channel read & write. 2.2.8. jtag interface tclk test clock tdi test data input tms test mode input tdo test data output 2.2.9. miscellaneous gpio[15:0] general purpose i/os spkrd speaker drive. this the output to the speaker and is an and of the counter 2 output with bit 1 of port 61, and drives an external speak- pin description 20/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. er driver. this output should be connected to 7407 type high voltage driver. scl, sda i2c interface . these bidirectional pins are connected to register 22h/23h index 97h. they conform to i 2 c electrical specifications, they have open-collector output drivers which are internally connected to v dd through pull-up resistors. scan_enable reserved . the pin is reserved for test and miscellaneous functions. vdd_core 2.5v core power supply. vdd 3.3v i/o power supply. vdd_pll pll power supplies. cpuclk pll, devclk pll, mckli pll, mclko pll, hclk pll. vss connected to gnd. pin description release 1.3 - january 29, 2002 21/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. .. table 2-4. isa / ide dynamic multiplexing isa bus (isaoe# = 0) ide (isaoe# = 1) rmrtccs# dd[15] kbcs# dd[14] rtcrw# dd[13] rtcds# dd[12] sa[19:8] dd[11:0] la[23] scs3# la[22] scs1# sa[21] pcs3# sa[20] pcs1# la[19:17] da[2:0] iochrdy diordy table 2-5. isa / local bus pin sharing isa / ipc local bus sd[15:0] pd[15:0] dreq_mux[1:0] pa[21:20] smemr# pa[19] memw# pa[18] bhe# pa[17] aen pa[16] ale pa[15] memr# pa[14] ior# pa[13] iow# pa[12] ref# pa[11] iochck# pa[10] gpiocs# pa[9] zws# pa[8] sa[7:4] pa[7:4] tc, dack_enc[2:0] pa[3:0] sa[3] prdy isaoe#,sa[2:0] iocs#[3:0] dev_clk, rtcas fcs#[1:0] iocs16#, master# prd#[1:0] smemw#, mcs16# pwr#[1:0] table 2-6. signal value on reset signal name sysrsti# active sysrsti# inactive sysrsto# active release of sysrsto# basic clocks and resets xtalo 14mhz isa_clk low 7mhz isa_clk2x, osc14m 14mhz gpclk 24mhz hclk oscillating at the speed defined by the strap options. pci_clko hclk divided by 2 or 3, depending on the strap options. memory controller mclko 66mhz if asynchonous mode, hclk speed if synchronized mode. cs#[3:1] high cs#[0] high sdram init sequence: write cycles ma[10:0], ba[0] 0x00 ras#[1:0], cas#[1:0] high mwe#, dqm[7:0] high md[63:0] input pci interface ad[31:0] 0x0000 first prefetch cycles when not in local bus mode. cbe[3:0], par low frame#, trdy#, irdy# input stop#, devsel# input serr# input pci_gnt#[2:0] high isa bus interface pin description 22/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. isaoe# high low rmrtccs# hi-z first prefetch cycles when in isa or pcmcia mode. address start is 0xfffff0 la[23:17] unknown 0x00 sa[19:0] 0xfffxx 0xfff03 sd[15:0] unknown 0xff bhe#, memr# unknown high memw#, smemr#, smemw#, ior#, iow# unknown high ref# unknown high ale, aen low dack_enc[2:0] input 0x04 tc input low gpiocs# hi-z high rtcds#, rtcrw#, kbcs# hi-z rtcas unknown low local bus interface pa[24:0] unknown first prefetch cycles pd[15:0] unknown 0xff prd# unknown high pbe#[1:0], fcs0#, fcs_0h# high fcs_0l#, fcs1#, fcs_1h#, fcs_1l# high pwr#, iocs#[7:0] high ide controller dd[15:0] 0xff da[2:0] unknown low pcs1, pcs3, scs1, scs3 unknown low pdack#, sdack# high pdior#, pdiow#, sdior#, sdiow# high i2c interface scl / ddc[1] input sda / ddc[0] input gpio signals gpio[15:0] high jtag tdo high miscellaneous spkrd low table 2-6. signal value on reset signal name sysrsti# active sysrsti# inactive sysrsto# active release of sysrsto# pin description release 1.3 - january 29, 2002 23/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. table 2-7. pinout. pin # pin name af3 sysrseti# ae4 sysrseto# a3 xtali c4 xtalo g23 hclk 2 h24 gp_clk af15 mclki ab23 mclko ae16 ma[0] ad15 ma[1] af16 ma[2] ae17 ma[3] ad16 ma[4] af17 ma[5] ae18 ma[6] ad17 ma[7] af18 ma[8] ae19 ma[9] ae20 ma[10] ac19 ba[0] af22 cs#[0] ad21 cs#[1] ae24 cs#[2]/ma[11] ad23 cs#[3]/ma[12]/ba[1] af23 ras#[0] ad22 ras#[1] ae21 cas#[0] ac20 cas#[1] af20 dqm#[0] ad19 dqm#[1] af21 dqm#[2] ad20 dqm#[3] ae22 dqm#[4] ae23 dqm#[5] af19 dqm#[6] ad18 dqm#[7] ac22 mwe# r1 md[0] 3 t2 md[1] 3 r3 md[2] t1 md[3] r4 md[4] u2 md[5] t3 md[6] u1 md[7] for note definition see table 2-2 definition of signal pins u4 md[8] 3 v2 md[9] 3 u3 md[10] v1 md[11] w2 md[12] v3 md[13] y2 md[14] w4 md[15] y1 md[16] w3 md[17] aa2 md[18] y4 md[19] aa1 md[20] y3 md[21] ab2 md[22] ab1 md[23] aa3 md[24] ab4 md[25] ac1 md[26] ab3 md[27] ad2 md[28] ac3 md[29] ad1 md[30] af2 md[31] af24 md[32] ae26 md[33] ad25 md[34] ad26 md[35] ac25 md[36] ac24 md[37] ac26 md[38] ab25 md[39] ab24 md[40] ab26 md[41] aa25 md[42] y23 md[43] aa24 md[44] aa26 md[45] y25 md[46] y26 md[47] y24 md[48] w25 md[49] 3 v23 md[50] 3 w26 md[51] 3 w24 md[52] 3 v25 md[53] 3 v26 md[54] 3 pin # pin name for note definition see table 2-2 definition of signal pins u25 md[55] 3 v24 md[56] 3 u26 md[57] 3 u23 md[58] 3 t25 md[59] 3 u24 md[60] 3 t26 md[61] 3 r25 md[62] 3 r26 md[63] 3 f24 pci_clki 2 d25 pci_clko b20 ad[0] c20 ad[1] b19 ad[2] a19 ad[3] c19 ad[4] b18 ad[5] a18 ad[6] b17 ad[7] c18 ad[8] a17 ad[9] d17 ad[10] b16 ad[11] c17 ad[12] b15 ad[13] a15 ad[14] c16 ad[15] b14 ad[16] d15 ad[17] a14 ad[18] b13 ad[19] d13 ad[20] a13 ad[21] c14 ad[22] b12 ad[23] c13 ad[24] a12 ad[25] c12 ad[26] a11 ad[27] d12 ad[28] b10 ad[29] c11 ad[30] a10 ad[31] d10 cbe[0] c10 cbe[1] a9 cbe[2] pin # pin name for note definition see table 2-2 definition of signal pins pin description 24/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. b8 cbe[3] a8 frame# b7 trdy# d8 irdy# a7 stop# c8 devsel# b6 par d7 serr# a6 lock# d20 pci_req#[0] c21 pci_req#[1] a21 pci_req#[2] c22 pci_gnt#[0] a22 pci_gnt#[1] b21 pci_gnt#[2] a5 pci_int[0] c6 pci_int[1] b4 pci_int[2] d5 pci_int[3] f2 la[17]/da[0] g4 la[18]/da[1] f3 la[19]/da[2] f1 la[20]/pcs1# g2 la[21]/pcs3# g1 la[22]/scs1# h2 la[23]/scs3# j4 sa[0] h1 sa[1] h3 sa[2] j2 sa[3] j1 sa[4] k2 sa[5] j3 sa[6] k1 sa[7] k4 sa[8] l2 sa[9] k3 sa[10] l1 sa[11] m2 sa[12] m1 sa[13] l3 sa[14] n2 sa[15] m4 sa[16] m3 sa[17] p2 sa[18] p4 sa[19] pin # pin name for note definition see table 2-2 definition of signal pins k25 sd[0] l24 sd[1] k26 sd[2] k23 sd[3] j25 sd[4] k24 sd[5] j26 sd[6] h25 sd[7] h26 sd[8] j24 sd[9] g25 sd[10] h23 sd[11] d24 sd[12] c26 sd[13] a25 sd[14] b24 sd[15] ad4 isa_clk af4 isa_clk2x c9 osc14m p25 ale ae8 zws# r23 bhe# p26 memr# r24 memw# n25 smemr# n23 smemw# n26 ior# p24 iow# n24 mcs16# m26 iocs16# m25 master# l25 ref# m24 aen l26 iochck# t24 iochrdy m23 isaoe# a4 rtcas p3 rtcds# r2 rtcrw# p1 rmrtccs# ae3 gpiocs# g26 pa[22] 2 a20 pa[23] b1 pirq pin # pin name for note definition see table 2-2 definition of signal pins c2 sirq c1 pdrq d2 sdrq d3 pdack# d1 sdack# e2 pdior# e4 pdiow# e3 sdior# e1 sdiow# e23 irq_mux[0] d26 irq_mux[1] e24 irq_mux[2] c25 irq_mux[3] a24 dreq_mux[0] b23 dreq_mux[1] c23 dack_enc[0] a23 dack_enc[1] b22 dack_enc[2] d22 tc n3 kbcs# ae5 gpio[0] ac5 gpio[1] ad5 gpio[2] af5 gpio[3] ae6 gpio[4] ac7 gpio[5] ad6 gpio[6] af6 gpio[7] ae7 gpio[8] af7 gpio[9] ad7 gpio[10] ad8 gpio[11] ae9 gpio[12] af9 gpio[13] ae10 gpio[14] ad9 gpio[15] c5 spkrd b5 scl c7 sda b3 scan_enable g3 tclk n1 tms w1 tdi ac2 tdo pin # pin name for note definition see table 2-2 definition of signal pins pin description release 1.3 - january 29, 2002 25/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. g24 vdd_cpuclk_pll 1 f25 vdd_devclk_pll 1 ac17 vdd_mclki_pll 1 ac15 vdd_mclko_pll 1 f26 vdd_hclk_pll 1 d11 vdd_core 1 l23 vdd_core 1 t4 vdd_core 1 ac6 vdd_core 1 d6 vdd d16 vdd d21 vdd f4 vdd f23 vdd l4 vdd t23 vdd aa4 vdd aa23 vdd ac11 vdd ac16 vdd ac21 vdd e25 vdd_pll_skew a1:2 vss a26 vss b2 vss b25:26 vss c3 vss c24 vss d4 vss d9 vss d14 vss d19 vss d23 vss h4 vss j23 vss l11:16 vss m11:16 vss n4 vss n11:16 vss p11:16 vss p23 vss r11:16 vss t11:16 vss v4 vss w23 vss ac4 vss pin # pin name for note definition see table 2-2 definition of signal pins ac8 vss ac13 vss ac18 vss ac23 vss ad3 vss ad14 vss ad24 vss ae1:2 vss ae25 vss af1 vss af25 vss af26 vss a16 unconnected b9 unconnected b11 unconnected c15 unconnected d18 unconnected e26 unconnected ac9 unconnected ac10 unconnected ac12 unconnected ac14 unconnected ad10 unconnected ad11 unconnected ad12 unconnected ad13 unconnected ae11 unconnected ae12 unconnected ae13 unconnected ae14 unconnected ae15 unconnected af8 unconnected af10 unconnected af11 unconnected af12 unconnected af13 unconnected af14 unconnected pin # pin name for note definition see table 2-2 definition of signal pins pin description 26/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. strap option release 1.3 - january 29, 2002 27/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 3. strap option this chapter defines the stpc ELITE strap options and their location. some strap options have been left programmable for future versions of silicon.. table 3-1. strap options signal designation actual settings 1 set to0 set to1 md2 hclk_pll speed user defined see section 3.1.4. bit 6 md3 user defined see section 3.1.4. bit 7 md4 pci_clko divisor user defined see section 3.1.1. bit 4 md5 mclk/hclk sync (see section 3.1.1. ) user defined async sync md6 pci_clko setup user defined see section 3.1.1. bit 6 md7 reserved pull down - - md10 reserved pull down - - md11 reserved pull down - - md16 reserved pull up - - md17 pci_clko divisor user defined see section 3.1.3. bit 1 md18 reserved pull up - - md19 reserved pull up - - md20 reserved pull up - - md21 reserved pull up - - md22 reserved pull up - - md23 reserved pull up - - md24 hclk pll speed user defined see section 3.1.4. bit 3 md25 user defined see section 3.1.4. bit 4 md26 user defined see section 3.1.4. bit 5 md27 reserved pull down md28 reserved pull down md29 reserved pull down md30 reserved pull down md40 cpu clock multiplication factor user defined x1 x2 md41 reserved pull down - - md42 reserved pull up - - md43 reserved pull down - - md44 bus select user defined isa local bus md45 reserved pull down - - md46 reserved pull up - - md47 reserved pull down - - md48 reserved pull up - - tc reserved pull up dack_enc[2:0] reserved pull up note 1 : where a strap is represented by a pull up or pull down, these have to be adhered to. if it is represented as a - it can be left unconnected. where user defined, the strap is set by the user. strap option 28/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 3.1. power on strap register descriptions 3.1.1. strap register 0 configuration strap0 access = 0022h/0023h regoffset = 04ah 76543210 md7 md6 md5 md4 md3 md2 rsv this register defaults to the values sampled on md[7:0] pins after reset bit number sampled mnemonic description bits 7-6 md[7:6] pciclk programming; the pciclk pll is setup through md[7:6]. the pll setup will vary depending on the pciclk frequency. see table 3-2 for details. bit 5 md5 this bit reflects the value sampled on md[5] pin and controls the mclk/ hclk synchronization. when mclk and hclk frequency are the same, when set to 1 it unifies hclk and mclk and so improves system performance. bit 4 md4 this bit reflects the value sampled on md[4] pin and controls the pciclko division. it works in conjunction with md[17]; refer to section 3.1.3. bit 1 for more details. bits 3-2 md[3:2] see section 3.1.4. bits 1-0 rsv reserved. table 3-2. pci clock programming bit 7 bit 6 description 0 0 pciclk frequency between 16 & 32 mhz 0 1 pciclk frequency between 32 & 64 mhz 1 x reserved strap option release 1.3 - january 29, 2002 29/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 3.1.2. strap register 1 configuration strap1 access = 0022h/0023h regoffset = 04bh 76543210 rsv md11 md10 rsv this register defaults to the values sampled on md[11:10] pins after reset bit number sampled mnemonic description bits 7-6 rsv reserved bits 5-4 rsv reserved bit 3 md11 reserved bit 2 md10 reserved bits 1-0 rsv reserved. strap option 30/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 3.1.3. strap register 2 configuration strap2 access = 0022h/0023h regoffset = 04ch 76543210 rsv md23 rsv md19 md18 md17 md16 this register defaults to the values sampled on md[23] and md[19:16] pins after reset bit number sampled mnemonic description bits 7-6 rsv reserved bit 5 md23 reserved bit 4 rsv reserved bit 3 md19 reserved bit 2 md18 reserved bit 1 md17 this bit, programmed in parallel with md[4], reflects the value sampled on md[17] pin and controls the pci clock output, as given in table 3-3 . bit 0 md16 reserved table 3-3. pci clock output md[4] md[17] description 0 x pci clock output = hclk / 4 1 0 pci clock output = hclk / 3 1 1 pci clock output = hclk / 2 strap option release 1.3 - january 29, 2002 31/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 3.1.4. hclk strap register configuration hclk_strap access = 0022h/0023h regoffset = 05fh 76543210 md3 md2 md26 md25 md24 rsv this register defaults to the values sampled on md[3:2] and md[26:24] pins after reset bit number sampled mnemonic description bits 7-3 md[3:2] & [26:24] these bits reflect the values sampled on md[3:2] and md[26:24] pins respectively and control the host clock frequency synthesizer, as given in table 3-4 . bits 2-0 rsv reserved table 3-4. hclk frequency bit 7 bit 6 bit 5 bit 4 bit 3 hclk frequency 00000 25 mhz 00001 50 mhz 00010 60 mhz 00011 66 mhz 01001 75 mhz 01110 82.5 mhz 10011 90 mhz 11001 100 mhz strap option 32/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. electrical specifications release 1.3 - january 29, 2002 33/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 4. electrical specifications 4.1. introduction the electrical specifications in this chapter are valid for the stpc ELITE. 4.2. electrical connections 4.2.1. power/ground connections/ decoupling due to the high frequency of operation of the stpc ELITE, it is necessary to install and test this device using standard high frequency techniques. the high clock frequencies used in the stpc ELITE and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. these effects can be minimized by filtering the dc power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the vss and vdd pins. 4.2.2. unused input pins no unused input pin should be left unconnected unless they have an integrated pull-up or pull- down. connect active-low inputs to vdd through a 20 k w (10%) pull-up resistor and active-high inputs to vss. for bi-directionnal active-high inputs, connect to vss through a 20 k w (10%) pull-up resistor to prevent spurious operation. 4.2.3. reserved designated pins pins designated as reserved should be left dis- connected. connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 4.3. absolute maximum ratings the following table lists the absolute maximum ratings for the stpc ELITE device. stresses beyond those listed under table 4-1 limits may cause permanent damage to the device. these are stress ratings only and do not imply that operation under any conditions other than those specified in section "operating conditions". exposure to conditions beyond those outlined in table 4-1 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. prolonged exposure to conditions at or near the absolute maximum ratings ( table 4-1 ) may also result in reduced useful life and reliability. 4.3.1. 5v tolerance the stpc is capable of running with i/o systems that operate at 5 v such as pci and isa devices. certain pins of the stpc tolerate inputs up to 5.5 v. above this limit the component is likely to sustain permanent damage. note 1: the figures specified apply to an stpc device that is soldered to a board, as detailed in the design guidelines section, for commercial and industrial tem- perature ranges. table 4-1. absolute maximum ratings symbol parameter minimum maximum units v ddx dc supply voltage -0.3 4.0 v v core dc supply voltage for core -0.3 2.7 v v i , v o digital input and output voltage -0.3 v dd + 0.3 v v 5t 5volt tolerance -0.3 5.5 v v esd esd capacity (human body mode) - 2000 v t stg storage temperature -40 +150 c t oper operating temperature (note 1) 0 +70 c -40 +85 c p tot maximum power dissipation (package) - 4.8 w electrical specifications 34/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 4.4. dc characteristics table 4-2. dc characteristics symbol parameter test conditions min typ max unit v dd 3.3v operating voltage 3.0 3.3 3.6 v v core 2.5v operating voltage 2.45 2.5 2.7 v p dd 3.3v supply power 3.0v < v dd < 3.6v 0.1 w p core 2.5v supply power 2.45v < v core < 2.7v 2.0 w v il input low voltage except xtali -0.3 0.8 v xtali -0.3 0.8 v v ih input high voltage except xtali 2.1 v dd +0.3 v xtali 2.35 v dd +0.3 v i lk input leakage current input, i/o -5 5 m a integrated pull up/down 50 k w table 4-3. pad buffers dc characteristics buffer type i/o count v ih min (v) v il max (v) v oh min (v) v ol max (v) i ol min (ma) i oh max (ma) c load max (pf) derating (ps/pf) 1 c in (pf) ana 1 2.35 0.9 - - - - - - - osci13b 1 2.1 0.8 2.4 0.4 2 - 2 50 - - bt8trp_tc 5 - - 2.4 0.4 8 - 8 200 21 6.89 bd4strp_ft 47 2 0.8 2.4 0.4 4 - 4 100 42 5.97 bd4strup_ft 10 2 0.8 2.4 0.4 4 - 4 100 41 5.97 bd8strp_ft 25 2 0.8 2.4 0.4 8 - 8 200 23 5.96 bd8strup_ft 55 2 0.8 2.4 0.4 8 - 8 200 23 5.96 bd8strp_tc 10 2 0.8 2.4 0.4 8 - 8 200 21 7.02 bd8trp_tc 45 2 0.8 2.4 0.4 8 - 8 200 21 7.03 bd8pciarp_ft 49 0.5*v dd 0.3*v dd 0.9*v dd 0.1*v dd 1.5 - 0.5 200 15 6.97 bd16staruqp_tc 19 2 0.8 2.4 0.4 16 -16 400 12 9.34 schmitt_ft 1 2 0.8 - - - - - - 5.97 tlcht_ft 2 2 0.8 - - - - - - 5.97 tlcht_tc 1 2 0.8 - - - - - - 5.97 tlchtd_tc 1 2 0.8 - - - - - - 5.97 note 1: time to output variation depending on the capacitive load. electrical specifications release 1.3 - january 29, 2002 35/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. note 1: pci clock at 33mhz table 4-4. 2.5v power consumptions (v core + vdd_x_pll) hclk (mhz) cpuclk (mhz) mclk (mhz) mode pmu (state) p max (w) v 2.5v =2.45v v 2.5v =2.7v 66 66 (x1) 66 sync stop clock 0.7 0.9 full speed 0.9 1.2 100 100 (x1) 100 stop clock 1.1 1.4 full speed 1.4 1.9 66 133 (x2) 66 stop clock 0.8 1.1 full speed 1.3 1.7 66 133 (x2) 100 async stop clock 1.0 1.4 full speed 1.5 2.0 table 4-5. 3.3v power consumptions (v dd ) hclk (mhz) cpuclk (mhz) mclk (mhz) pmu (state) p max (mw) 66 66 (x1) 66 full speed 70 100 100 (x1) 100 90 66 133 (x2) 66 80 66 133 (x2) 100 100 table 4-6. pll power consumptions pll name p max (mw) vdd_pll = 2.45v vdd_pll = 2.7v vdd_gpclk_pll 5 10 vdd_hclki_pll 5 10 vdd_hclko_pll 5 10 vdd_mclki_pll 5 10 vdd_mclko_pll 5 10 vdd_pciclk_pll 5 10 electrical specifications 36/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 4.5. ac characteristics this section lists the ac characteristics of the stpc interfaces including output delays, input setup requirements, input hold requirements and output float delays. these measurements are based on the measurement points identified in figure 4-1 and figure 4-2 . the rising clock edge reference level vref and other reference levels are shown in table 4-7 below. input or output signals must cross these levels during testing. figure 4-1 shows output delay (a and b) and input setup and hold times (c and d). input setup and hold times (c and d) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation. note: refer to figure 4-1 . table 4-7. drive level and measurement points for switching characteristics symbol value units v ref 1.5 v v ihd 2.5 v v ild 0.0 v figure 4-1. drive level and measurement points for switching characteristics clk: v ref v ild v ihd tx legend: a - maximum output delay specification b - minimum output delay specification c - minimum input setup specification d - minimum input hold specification v ref valid valid valid outputs: inputs: output n output n+1 input max min a b cd v ref v ild v ihd electrical specifications release 1.3 - january 29, 2002 37/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. figure 4-2. clk timing measurement points clk t5 t4 t3 v ref v il (max) v ih (min) t2 t1 legend: t1 - one clock cycle t2 - minimum time at v ih t3 - minimum time at v il t4 - clock fall time t5 - clock rise time note; all signals are sampled on the rising edge of the clk. electrical specifications 38/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 4.5.1. power on sequence figure 4-3 describes the power-on sequence of the stpc, also called cold reset. there is no dependency between the different power supplies and there is no constraint on their rising time. sysrsti# as no constraint on its rising edge but must stay active until power supplies are all within specifications, a margin of 10 m s is even recommended to let the stpc plls and strap options stabilize. strap options are continuously sampled during sysrsti# low and must remain stable. once sysrsti# is high, they must not change until sysrsto# goes high. bus activity starts only few clock cycles after the release of sysrsto#. the t oggling signals depend on the stpc configuration. in isa mode, activity is visible on pci prior to the isa bus as the controller is part of the south bridge. in local bus mode, the pci bus is not accessed and the flash chip select is the control signal to monitor. figure 4-3. power-on timing diagram strap options power supplies sysrsti# sysrsto# 14 mhz 1.6 v valid configuration > 10 us hclk pci_clk 2.3 ms isaclk electrical specifications release 1.3 - january 29, 2002 39/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 4.5.2 reset sequence figure 4-4 describes the reset sequence of the stpc, also called warm reset. the constraints on the strap options and the bus activities are the same as for the cold reset. the sysrsti# pulse duration must be long enough to have all the strap options stabilized and must be adjusted depending on resistor values. it is mandatory to have a clean reset pulse without glitches as the stpc could then sample invalid strap option setting and enter into an umpredicta- ble mode. while sysrsti# is active, the pci clock pll runs in open loop mode at a speed of few 100s khz. fi g ure 4-4. reset timin g dia g ram strap options sysrsti# sysrsto# 14 mhz valid configuration hclk pci_clk 2.3 ms isaclk 1.6 v md[63:0] electrical specifications 40/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 4.5.3. sdram interface figure 4-5 and table 4-8 list the ac characteris- tics of the sdram interface. the mclkx clocks are the input clock of the sdram devices the pc133 memory is recommended to reach 100mhz operation. figure 4-5. sdram timing diagram mclki stpc.output stpc.input mclkx t delay t setup t hold t output (min) t output (max) t cycle t high t low table 4-8. sdram bus ac timing name parameter min typ max unit tcycle mclki cycle time 10 ns thigh mclki high time 4 ns tlow mclki low time 4 ns mclki rising time 1 ns mclki falling time 1 ns tdela y mclkx to mclki dela y -2 ns toutput mclki to outputs valid 5.2 8.7 ns mclki to dqm[ ] outputs valid 4.7 10.9 ns mclki to md[ ] outputs valid 5.1 10.9 ns tsetup md[63:0] setup to mckli without rdclk 0.8 1.8 ns thold md[63:0] hold from mckli without rdclk 0.8 1.6 ns note: these timing are for a load of 50pf. electrical specifications release 1.3 - january 29, 2002 41/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 4.5.4. pci interface table 4-9 lists the ac characteristics of the pci in- terface. table 4-9. pci bus ac timing name parameter min max unit pci_clki to ad[31:0] valid - 9.3 ns pci_clki to frame valid - 7.14 ns pci_clki to cbe [3:0] valid - 7.94 ns pci_clki to par valid - 9.34 ns pci_clki to trdy valid - 8.8 ns pci_clki to irdy valid - 7.74 ns pci_clki to stop valid - 9.4 ns pci_clki to devsel valid - 8.5 ns pci_clki to pci_gnt valid - 7.14 ns ad[31:0] bus setup to pci_clki 5.42 ns frame setup to pci_clki 5.03 ns cbe [3:0] setup to pci_clki 6.37 ns irdy setup to pci_clki 4.52 ns pci_req [2:0] setup to pci_clki 5.29 ns ad[31:0] bus hold from pci_clki -0.91 ns frame hold from pci_clki -1.8 ns cbe [3:0] hold to pci_clki -2.9 ns irdy hold to pci_clki -1.6 ns pci_req [2:0] hold from pci_clki -3.49 ns electrical specifications 42/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 4.5.5 ipc interface table 4-10 lists the ac characteristics of the ipc interface. figure 4-6. ipc timing diagram isaclk irq_mux[3:0] dreq_mux[1:0] isaclk2x t dly t setup t setup table 4-10. ipc interface ac timings name parameter min max unit t dly isaclk2x to isaclk delay ns isaclk2x to dack_enc[2:0] valid ns isaclk2x to tc valid ns t setup irq_mux[3:0] input setup to isaclk2x 0 - ns t setup dreq_mux[1:0] input setup to isaclk2x 0 - ns electrical specifications release 1.3 - january 29, 2002 43/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 4.5.6 isa interface ac timing characteristics table 4-7 and table 4-11 list the ac characteris- tics of the isa interface. figure 4-7 isa cycle (ref table 4-11 ) note 1: stands for smemr#, smemw#, memr#, memw#, ior# & iow#. the clock has not been represented as it is dependent on the isa slave mode. valid aenx valid address valid address, sbhe* v.dat a valid data 54 28 26 64 59 58 55 28 23 61 48 47 26 23 57 27 24 42 41 10 11 34 33 3 22 56 29 25 9 18 2 12 38 37 15 14 13 12 ale aen la [23:17] sa [19:0] control (note 1) iocs16# mcs16# iochrdy read data write data table 4-11. isa bus ac timing name parameter min max units 2 la[23:17] valid before ale# negated 5t cycles 3 la[23:17] valid before memr#, memw# asserted 3a memory access to 16-bit isa slave 5t cycles 3b memory access to 8-bit isa slave 5t cycles 9 sa[19:0] & sbhe valid before ale# negated 1t cycles 10 sa[19:0] & sbhe valid before memr#, memw# asserted 10a memory access to 16-bit isa slave 2t cycles 10b memory access to 8-bit isa slave 2t cycles 10 sa[19:0] & shbe valid before smemr#, smemw# asserted 10c memory access to 16-bit isa slave 2t cycle note: the signal numbering refers to table 4-7 electrical specifications 44/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 10d memory access to 8-bit isa slave 2t cycle 10e sa[19:0] & sbhe valid before ior#, iow# asserted 2t cycles 11 isaclk2x to iow# valid 11a memory access to 16-bit isa slave - 2bclk 2t cycles 11b memory access to 16-bit isa slave - standard 3bclk 2t cycles 11c memory access to 16-bit isa slave - 4bclk 2t cycles 11d memory access to 8-bit isa slave - 2bclk 2t cycles 11e memory access to 8-bit isa slave - standard 3bclk 2t cycles 12 ale# asserted before ale# negated 1t cycles 13 ale# asserted before memr#, memw# asserted 13a memory access to 16-bit isa slave 2t cycles 13b memory access to 8-bit isa slave 2t cycles 13 ale# asserted before smemr#, smemw# asserted 13c memory access to 16-bit isa slave 2t cycles 13d memory access to 8-bit isa slave 2t cycles 13e ale# asserted before ior#, iow# asserted 2t cycles 14 ale# asserted before al[23:17] 14a non compressed 15t cycles 14b compressed 15t cycles 15 ale# asserted before memr#, memw#, smemr#, smemw# negated 15a memory access to 16-bit isa slave- 4 bclk 11t cycles 15e memory access to 8-bit isa slave- standard cycle 11t cycles 18a ale# negated before la[23:17] invalid (non compressed) 14t cycles 18a ale# negated before la[23:17] invalid (compressed) 14t cycles 22 memr#, memw# asserted before la[23:17] 22a memory access to 16-bit isa slave. 13t cycles 22b memory access to 8-bit isa slave. 13t cycles 23 memr#, memw# asserted before memr#, memw# negated 23b memory access to 16-bit isa slave standard cycle 9t cycles 23e memory access to 8-bit isa slave standard cycle 9t cycles 23 smemr#, smemw# asserted before smemr#, smemw# negated 23h memory access to 16-bit isa slave standard cycle 9t cycles 23l memory access to 16-bit isa slave standard cycle 9t cycles 23 ior#, iow# asserted before ior#, iow# negated 23o memory access to 16-bit isa slave standard cycle 9t cycles 23r memory access to 8-bit isa slave standard cycle 9t cycles 24 memr#, memw# asserted before sa[19:0] 24b memory access to 16-bit isa slave standard cycle 10t cycles 24d memory access to 8-bit isa slave - 3blck 10t cycles 24e memory access to 8-bit isa slave standard cycle 10t cycles 24f memory access to 8-bit isa slave - 7bclk 10t cycles 24 smemr#, smemw# asserted before sa[19:0] 24h memory access to 16-bit isa slave standard cycle 10t cycles 24i memory access to 16-bit isa slave - 4bclk 10t cycles 24k memory access to 8-bit isa slave - 3bclk 10t cycles 24l memory access to 8-bit isa slave standard cycle 10t cycles table 4-11. isa bus ac timing name parameter min max units note: the si g nal numberin g refers to table 4-7 electrical specifications release 1.3 - january 29, 2002 45/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 24 ior#, iow# asserted before sa[19:0] 24o i/o access to 16-bit isa slave standard cycle 19t cycles 24r i/o access to 16-bit isa slave standard cycle 19t cycles 25 memr#, memw# asserted before next ale# asserted 25b memory access to 16-bit isa slave standard cycle 10t cycles 25d memory access to 8-bit isa slave standard cycle 10t cycles 25 smemr#, smemw# asserted before next ale# asserted 25e memory access to 16-bit isa slave - 2bclk 10t cycles 25f memory access to 16-bit isa slave standard cycle 10t cycles 25h memory access to 8-bit isa slave standard cycle 10t cycles 25 ior#, iow# asserted before next ale# asserted 25i i/o access to 16-bit isa slave standard cycle 10t cycles 25k i/o access to 16-bit isa slave standard cycle 10t cycles 26 memr#, memw# asserted before next memr#, memw# asserted 26b memory access to 16-bit isa slave standard cycle 12t cycles 26d memory access to 8-bit isa slave standard cycle 12t cycles 26 smemr#, smemw# asserted before next smemr#, smemw# asserted 26f memory access to 16-bit isa slave standard cycle 12t cycles 26h memory access to 8-bit isa slave standard cycle 12t cycles 26 ior#, iow# asserted before next ior#, iow# asserted 26i i/o access to 16-bit isa slave standard cycle 12t cycles 26k i/o access to 8-bit isa slave standard cycle 12t cycles 28 any command negated to memr#, smemr#, memr#, smemw# asserted 28a memory access to 16-bit isa slave 3t cycles 28b memory access to 8-bit isa slave 3t cycles 28 any command negated to ior#, iow# asserted 28c i/o access to isa slave 3t cycles 29a memr#, memw# negated before next ale# asserted 1t cycles 29b smemr#, smemw# negated before next ale# asserted 1t cycles 29c ior#, iow# negated before next ale# asserted 1t cycles 33 la[23:17] valid to iochrdy negated 33a memory access to 16-bit isa slave - 4 bclk 8t cycles 33b memory access to 8-bit isa slave - 7 bclk 14t cycles 34 la[23:17] valid to read data valid 34b memory access to 16-bit isa slave standard cycle 8t cycles 34e memory access to 8-bit isa slave standard cycle 14t cycles 37 ale# asserted to iochrdy# negated 37a memory access to 16-bit isa slave - 4 bclk 6t cycles 37b memory access to 8-bit isa slave - 7 bclk 12t cycles 37c i/o access to 16-bit isa slave - 4 bclk 6t cycles 37d i/o access to 8-bit isa slave - 7 bclk 12t cycles 38 ale# asserted to read data valid 38b memory access to 16-bit isa slave standard cycle 4t cycles 38e memory access to 8-bit isa slave standard cycle 10t cycles 38h i/o access to 16-bit isa slave standard cycle 4t cycles 38l i/o access to 8-bit isa slave standard cycle 10t cycles table 4-11. isa bus ac timing name parameter min max units note: the signal numbering refers to table 4-7 electrical specifications 46/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 41 sa[19:0] sbhe valid to iochrdy negated 41a memory access to 16-bit isa slave 6t cycles 41b memory access to 8-bit isa slave 12t cycles 41c i/o access to 16-bit isa slave 6t cycles 41d i/o access to 8-bit isa slave 12t cycles 42 sa[19:0] sbhe valid to read data valid 42b memory access to 16-bit isa slave standard cycle 4t cycles 42e memory access to 8-bit isa slave standard cycle 10t cycles 42h i/o access to 16-bit isa slave standard cycle 4t cycles 42l i/o access to 8-bit isa slave standard cycle 10t cycles 47 memr#, memw#, smemr#, smemw#, ior#, iow# asserted to iochrdy negated 47a memory access to 16-bit isa slave 2t cycles 47b memory access to 8-bit isa slave 5t cycles 47c i/o access to 16-bit isa slave 2t cycles 47d i/o access to 8-bit isa slave 5t cycles 48 memr#, smemr#, ior# asserted to read data valid 48b memory access to 16-bit isa slave standard cycle 2t cycles 48e memory access to 8-bit isa slave standard cycle 5t cycles 48h i/o access to 16-bit isa slave standard cycle 2t cycles 48l i/o access to 8-bit isa slave standard cycle 5t cycles 54 iochrdy asserted to read data valid 54a memory access to 16-bit isa slave 1t(r)/2t(w) cycles 54b memory access to 8-bit isa slave 1t(r)/2t(w) cycles 54c i/o access to 16-bit isa slave 1t(r)/2t(w) cycles 54d i/o access to 8-bit isa slave 1t(r)/2t(w) cycles 55a iochrdy asserted to memr#, memw#, smemr#, smemw#, ior#, iow# negated 1t cycles 55b iochry asserted to memr#, smemr# negated (refresh) 1t cycles 56 iochrdy asserted to next ale# asserted 2t cycles 57 iochrdy asserted to sa[19:0], sbhe invalid 2t cycles 58 memr#, ior#, smemr# negated to read data invalid 0t cycles 59 memr#, ior#, smemr# negated to data bus float 0t cycles 61 write data before memw# asserted 61a memory access to 16-bit isa slave 2t cycles 61b memory access to 8-bit isa slave (byte copy at end of start) 2t cycles 61 write data before smemw# asserted 61c memory access to 16-bit isa slave 2t cycles 61d memory access to 8-bit isa slave 2t cycles 61 write data valid before iow# asserted 61e i/o access to 16-bit isa slave 2t cycles 61f i/o access to 8-bit isa slave 2t cycles 64a memw# negated to write data invalid - 16-bit 1t cycles 64b memw# negated to write data invalid - 8-bit 1t cycles 64c smemw# negated to write data invalid - 16-bit 1t cycles 64d smemw# negated to write data invalid - 8-bit 1t cycles table 4-11. isa bus ac timing name parameter min max units note: the si g nal numberin g refers to table 4-7 electrical specifications release 1.3 - january 29, 2002 47/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 64e iow# negated to write data invalid 1t cycles 64f memw# negated to copy data float, 8-bit isa slave, odd byte by isa master 1t cycles 64g iow# negated to copy data float, 8-bit isa slave, odd byte by isa master 1t cycles table 4-11. isa bus ac timing name parameter min max units note: the signal numbering refers to table 4-7 electrical specifications 48/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 4.5.7 local bus interface figure 4-3 to figure 4-11 and table 4-13 list the ac characteristics of the local bus interface. figure 4-8. synchronous read cycle pa[ ] bus csx# prd#[1:0] pd[15:0] hclk t setup t active t hold figure 4-9. asynchronous read cycle pa[ ] bus csx# prd#[1:0] pd[15:0] hclk t setup t end t hold prdy electrical specifications release 1.3 - january 29, 2002 49/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. figure 4-10. synchronous write cycle pa[ ] bus csx# pwr#[1:0] pd[15:0] hclk t setup t active t hold figure 4-11. asynchronous write cycle pa[ ] bus csx# pwr#[1:0] pd[15:0] hclk t setup t end t hold prdy electrical specifications 50/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. the table 4-12 below refers to vh, va, vs which are the register value for setup time, active time and hold time, as described in the programming manual. table 4-12. local bus cycle lenght cycle t setup t active t hold t end unit memory (fcsx#) 4 + vh 2 + va 4 + vs 4 hclk peripheral (iocsx#) 8 + vh 3 + va 4 + vs 4 hclk table 4-13. local bus interface ac timing name parameters min max units hclk to pa bus - 15 ns hclk to pd bus - 15 ns hclk to fcs#[1:0] - 15 ns hclk to iocs#[3:0] - 15 ns hclk to pwr#[1:0] - 15 ns hclk to prd#[1:0] - 15 ns pd[15:0] input setup to hclk - 4 ns pd[15:0] input hold to hclk 2 - ns prdy input setup to hclk - 4 ns prdy input hold to hclk 2 - ns electrical specifications release 1.3 - january 29, 2002 51/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 4.5.8. ide interface table 4-14 lists the ac characteristics of the ide interface. table 4-14. ide interface timing name parameters min max units dd[15:0] setup to pior#/sior# falling 15 - ns dd[15:0} hold to pior#/sior# falling 0 - ns electrical specifications 52/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 4.5.9 jtag interface figure 4-12 and table 4-15 list the ac characteristics of the jtag interface. figure 4-12. jtag timing diagram table 4-15. jtag ac timings name parameter min max unit treset trst pulse width 1 tcycle tcycle tclk period 400 ns tclk rising time 20 ns tclk falling time 20 ns tjset tms setup time 200 ns tjhld tms hold time 200 ns tjset tdi setup time 200 ns tjhld tdi hold time 200 ns tjout tclk to tdo valid 30 ns tpset stpc pin setup time 30 ns tphld stpc pin hold time 30 ns tpout tclk to stpc pin valid 30 ns tck stpc.input trst t reset t cycle stpc.output tms,tdi tdo t jset t jhld t jout t pset t phld t pout mechanical data release 1.3 - january 29, 2002 53/87 5. mechanical data 5.1. 388-pin package dimension the pin numbering for the stpc 388-pin plastic bga package is shown in figure 5-1 . dimensions are shown in figure 5-2 , table 5-1 and figure 5-3 , table 5-2 . figure 5-1. 388-pin pbga package - top view a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 135791113151719212325 2 4 6 8 10 12 14 16 18 20 22 24 26 a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 135791113151719212325 2468101214161820222426 mechanical data 54/87 release 1.3 - januar y 29, 2002 figure 5-2. 388-pin pbga package - pcb dimensions table 5-1. 388-pin pbga package - pcb dimensions symbols mm inches min typ max min typ max a 34.95 35.00 35.05 1.375 1.378 1.380 b 1.22 1.27 1.32 0.048 0.050 0.052 c 0.58 0.63 0.68 0.023 0.025 0.027 d 1.57 1.62 1.67 0.062 0.064 0.066 e 0.15 0.20 0.25 0.006 0.008 0.001 f 0.05 0.10 0.15 0.002 0.004 0.006 g 0.75 0.80 0.85 0.030 0.032 0.034 a a b detail a1 ball pad corner d f e g c mechanical data release 1.3 - january 29, 2002 55/87 figure 5-3. 388-pin pbga package - dimensions table 5-2. 388-pin pbga package - dimensions symbols mm inches min typ max min typ max a 0.50 0.56 0.62 0.020 0.022 0.024 b 1.12 1.17 1.22 0.044 0.046 0.048 c 0.60 0.76 0.92 0.024 0.030 0.036 d 0.52 0.53 0.54 0.020 0.021 0.022 e 0.63 0.78 0.93 0.025 0.031 0.037 f 0.60 0.63 0.66 0.024 0.025 0.026 g 30.0 11.8 a b c solderball solderball after collapse d e f g mechanical data 56/87 release 1.3 - januar y 29, 2002 5.2. 388-pin package thermal data the 388-pin pbga package has a power dissipation capability of 4.5w. this increases to 6w when used with a heatsink. the structure in shown in fi g ure 5-4 . thermal dissipation options are illustrated in fi g ure 5-5 and fi g ure 5-6 . figure 5-4. 388-pin pbga structure thermal balls power & ground layers signal layers figure 5-5. thermal dissipation without heatsink ambient board case junction board ambient ambient case junction board rca rjc rjb rba 66 125 8.5 rja = 13 c/w airflow = 0 board dimensions: the pbga is centred on board copper thickness: - 17m for internal layers - 34m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the centrecentre b a mechanical data release 1.3 - january 29, 2002 57/87 figure 5-6. thermal dissipation with heatsink board ambient case junction board ambient ambient case junction board rca rjc rjb rba 36 50 8.5 rja = 9.5 c/w airflow = 0 board dimensions: the pbga is centred on board copper thickness: - 17m for internal layers - 34m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices heat sink is 11.1c/w 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the centre balls mechanical data 58/87 release 1.3 - januar y 29, 2002 5.3. soldering recommendations high quality, low defect soldering requires identifying the optimum temperature profile for reflowing the solder paste, therefore optimizing the process. the heating and cooling rise rates must be compatible with the solder paste and components. a typical profile consists of a preheat, dryout, reflow and cooling sections. the most critical parameter in the preheat section is to minimize the rate of temperature rise to less than 2 c / second, in order to minimize thermal shock on the semi-conductor components. dryout section is used primarily to ensure that the solder paste is fully dried before hitting reflow temperatures. solder reflow is accomplished in the reflow zone , where the solder paste is elevated to a temperature greater than the melting point of the solder. melting temperature must be exceeded by approximately 20 c to ensure quality reflow. in reality the profile is not a line, but rather a range of temperatures all solder joints must be exposed. the total temperature deviation from component thermal mismatch, oven loading and oven uniformity must be within the band. figure 5-7. reflow soldering temperature range temperature ( c ) time ( s ) preheat dryout reflow cooling 240 0 250 200 150 100 50 0 design guidelines release 1.3 - january 29, 2002 59/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6. design guidelines 6.1. typical applications the stpc ELITE is well suited for many display- less applications or together with a pci graphics/ video device. some of the possible implementations are described below. 6.1.1. file server a file server is lan hot-pluggable system that enables the user to obtain additionnal disk capacity with great flexibility. figure 6-1. file server stpc ELITE sdram 64 flash lan 16 pci ide design guidelines 60/87 release 1.3 - january 29, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.2. stpc configuration the stpc is a very flexible product thanks to decoupled clock domains and to strap options enabling a user-optimized configuration. as some trade off are often necessary, it is important to do an analysis of the application needs prior to design a system based on this product. the applicative constraints are usually the following: - cpu performance - graphics / video performances - power consumption - pci bandwidth - booting time - emc some other elements can help to tune the choice: - code size of cpu consuming tasks - data size and location on the stpc side, the configurable parameters are the following: - synchronous / asynchronous mode - hclk speed - mclk speed - cpu clock ratio (x1, x2) - local bus / isa bus 6.2.1. local bus / isa bus the selection between the isa bus and the local bus is relatively simple. the first one is a standard bus but slow. the local bus is fast and programmable but doesn't support any dma nor external master mechanisms. the table 6-1 below summarize the selection: before implementing a function requiring dma capability on the isa bus, it is recommended to check if it exists on pci, or if it can be implemented differently, in order to use the local bus mode. 6.2.2. clock configuration the cpu clock and the memory clock are independent unless the "synchronous mode" strap option is set (see the strap options chapter). the potential clock configurations are then relatively limited as listed in table 6-2 . the advantage of the synchronous mode compared to the asynchronous mode is a lower latency when accessing sdram from the cpu or the pci (saves 4 mclk cycles for the first access of the burst). for the same cpu to memory transfer performance, mclk as to be roughly higher by 20mhz between sync and async modes (example: 66mhz sync = 96mhz async). in all cases, use sdram with cas latency equals to 2 (cl2) for the best performances. the advantage of the asynchronous mode is the capability to reprogram the mclk speed on the fly. this could help for applications were power consumption must be optimized. regarding pci bandwidth, the best is to have hclk at 100mhz as it gives twice the bandwidth compared to hclk at 66mhz. the last, and more complex, information to consider is the behaviour of the software. in case high cpu or fpu computation is needed, it is sometime better to be in dx2-133/mclk=66 synchronous mode than dx2-133/mclk=100 asynchronous mode. this depends on the locality of the number crunching code and the amount of data manipulated. the table 6-3 below gives some examples. the right column correspond to the configuration number as described in table 6-2 : obviously, the values for hclk or mclk can be reduced compared to table 6-2 in case there is no need to push the device at its limits, or when avoiding to use specific frequency ranges (fm radio band for example). table 6-1. bus mode selection need selection legacy i/o device (floppy, ...), super i/o isa bus dma capability (soundblaster) isa bus flash, sram, basic i/o device local bus fast boot local bus boot flash of 4mb or more local bus programmable chip select local bus table 6-2. main stpc modes cmode hclk mhz cpu clock clock ratio mclk mhz 1 synchronous 66 133 (x2) 66 2 asynchronous 66 133 (x2) 100 3 synchronous 100 100 (x1) 100 table 6-3. clock mode selection constraints c need cpu power critical code fits into l1 cache 1 need cpu power code or data does not fit into l1 cache 3 need high pci bandwitdh 3 need flexible sdram speed 2 design guidelines release 1.3 - january 29, 2002 61/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.3. architecture recommendations this section describes the recommend implementations for the stpc interfaces. for more details, download the reference schematics from the stpc web site. 6.3.1. power decoupling an appropriate decoupling of the various stpc power pins is mandatory for optimum behaviour. when insufficient, the integrity of the signals is deteriorated, the stability of the system is reduced and emc is increased. 6.3.1.1. pll decoupling this is the most important as the stpc clocks are generated from a single 14mhz stage using multiple plls which are highly sensitive analog cells. the frequencies to filter are the 25-50 khz range which correspond to the internal loop bandwidth of the pll and the 10 to 100 mhz frequency of the output. pll power pins can be tied together to simplify the board layout. 6.3.1.2. decoupling of 3.3v and vcore a power plane for each of these supplies with one decoupling capacitance for each power pin is the minimum. the use of multiple capacitances with values in decade is the best (for example: 10pf, 1nf, 100nf, 10uf), the smallest value, the closest to the power pin. connecting the various digital power planes through capacitances will reduce furthermore the overall impedance and electrical noise. 6.3.2. 14mhz oscillator stage the 14.31818 mhz oscillator stage can be implemented using a quartz, which is the preferred and cheaper solution, or using an external 3.3v oscillator. the crystal must be used in its series-cut fundamental mode and not in overtone mode. it must have an equivalent series resistance (esr, sometimes referred to as rm) of less than 50 ohms (typically 8 ohms) and a shunt capacitance (co) of less than 7 pf. the balance capacitors of 16 pf must be added, one connected to each pin, as described in figure 6-3 . in the event of an external oscillator providing the master clock signal to the stpc atlas device, the lvttl signal should be connected to xtali, as described in figure 6-3 . as this clock is the reference for all the other on- chip generated clocks, it is strongly recommended to shield this stage , including the 2 wires going to the stpc balls, in order to reduce the jitter to the minimum and reach the optimum system stability. figure 6-2. pll decoupling vdd_pll vss_pll pwr 100nf 47uf gnd connections must be as short as possible figure 6-3. 14.31818 mhz stage 15pf 15pf xtalo xtali xtalo xtali 3.3v design guidelines 62/87 release 1.3 - january 29, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.3.3. sdram the stpc provides all the signals for sdram control. up to 128 mbytes of main memory are supported. all banks must be 64 bits wide. up to 4 memory banks are available when using 16mbit devices. only up to 2 banks can be connected when using 64mbit and 128mbit components due to the reallocation of cs2# and cs3# signals. this is described in table 6-4 and table 6-5 . graphics memory resides at the beginning of bank 0. host memory begins at the top of graphics memory and extends to the top of populated sdram. bank 0 must always be populated. figure 6-4 , figure 6-5 and figure 6-6 show some typical implementations. the purpose of the serial resistors is to reduce signal oscillation and emi by filtering line reflections. the capacitance in figure 6-4 has a filtering effect too, while it is used for propagation delay compensation in the 2 other figures. figure 6-4. one memory bank with 4 chips (16-bit) cs0# ba[1:0] ma[12:0] we# ras0# dqm[7:0] mclki mclko dqm[7:6] reference knot cas0# md[63:48] dqm[5:4] md[47:32] dqm[3:2] md[31:16] dqm[1:0] md[15:0] md[63:0] mclka mclkb mclkc mclkd 10pf length(mclki) = length(mclky) with y = {a,b,c,d} design guidelines release 1.3 - january 29, 2002 63/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. figure 6-5. one memory banks with 8 chips (8-bit) figure 6-6. two memory banks with 8 chips (8-bit) cs0# ba[1:0] ma[12:0] we# ras0# dqm[7:0] mclki mclko dqm[7] cas0# md[63:56] dqm[0] md[7:0] md[63:0] a 10pf length(mclki) = length(mclky) with y = {a,b,c,d,e,f,g,h} dqm[1] md[15:8] b c d e f g h cy2305 cs1# ba[1:0] ma[12:0] we# ras0# dqm[7:0] mclki mclko dqm[7] cas0# md[63:56] dqm[0] md[7:0] md[63:0] a 1 22pf length(mclki) = length(mclky x ) with dqm[1] md[15:8] b 1 c 1 d 1 e 1 f 1 g 1 h 1 cs0# a 0 b 0 c 0 d 0 e 0 f 0 g 0 h 0 x = {0,1} y = {a,b,c,d,e,f,g,h} cy2305 design guidelines 64/87 release 1.3 - january 29, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. for other implementations like 32-bit sdram devices, refers to the sdram controller signal multiplexing and address mapping described in the following table 6-4 and table 6-5 . table 6-4. dimm pinout sdram density 16 mbit 64/128 mbit 64/128 mbit stpc i/f internal banks 2 banks 2 banks 4 banks dimm pin number ... ma[10:0] ma[10:0] ma[10:0] ma[10:0] 123 - ma11 ma11 cs2# (ma11) 126 - ma12 - cs3# (ma12) 39 - - ba1 (ma12) cs3# (ba1) 122 ba0 (ma11) ba0 (ma13) ba0 (ma13) ba0 table 6-5. address mapping address mapping: 16 mbit - 2 internal banks stpc i/f ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras address a11 a22 a21 a2 a19 a18 a17 a16 a15 a14 a13 a12 cas address a11 0 a24 a23 a10 a9 a8 a7 a6 a5 a4 a3 address mapping: 64/128 mbit - 2 internal banks stpc i/f ba0 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras address a11 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 cas addressa110 0 0 a26a25a10a9a8a7a6a5a4a3 address mapping: 64/128 mbit - 4 internal banks stpc i/f ba0 ba1 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras address a11 a12 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 cas address a11 a12 0 0 a26 a25 a10 a9 a8 a7 a6 a5 a4 a3 design guidelines release 1.3 - january 29, 2002 65/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.3.4. pci bus the pci bus is always active and the following control signals must be pulled-up to 3.3v or 5v through 2k2 resistors even if this bus is not connected to an external device: frame#, trdy#, irdy#, stop#, devsel#, lock#, serr#, pci_req#[2:0]. pci_clko must be connected to pci_clki through a 10 to 33 ohms resistor. figure 6-7 shows a typical implementation. for more information on layout constraints, go to the place and route recommendations section. in the case of higher clock load it is recommended to use a zero-delay clock buffer as described in figure 6-8 . this approach is also recommended when implementing the delay on pciclki according to the pci section of the electrical specifications chapter. figure 6-7. typical pci clock routing pciclki pciclko pciclka pciclkb pciclkc 0 - 22 10 - 33 device a device b device c 0 - 33pf figure 6-8. pci clock routing with zero-delay clock buffer pciclki pciclko device a device b device c pll device d pciclki pciclko device a device b device c pll device d cy2305 cy2305 implementation 1 implementation 2 design guidelines 66/87 release 1.3 - january 29, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.3.5. local bus the local bus has all the signals to connect flash devices or i/o devices with the minimum glue logic. figure 6-9 describes how to connect a 16-bit boot flash (the corresponding strap options must be set accordingly). fi g ure 6-9. typical 16-bit boot flash implementation m58lw064a stpc 22 dq[15:0] a[22:1] ce oe w rp b clk rb le r 3v3 gnd reset# 16 pd[15:0] fcs0# pwr0# sysrsti# prd0# pa[22:1] prd1# pwr1# design guidelines release 1.3 - january 29, 2002 67/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.3.6. ipc most of the ipc signals are multiplexed: interrupt inputs, dma request inputs, dma acknowledge outputs. the figure below describes a complete implementation of the irq[15:0] time-multiplexing. when an interrupt line is used internally, the corresponding input can be grounded. in most of the embedded designs, only few interrupts lines are necessary and the glue logic can be simplified. when the interface is integrated into the stpc, the corresponding interrupt line can be grounded as it is connected internally. for example, if the integrated ide controller is activated, the irq[14] and irq[15] inputs can be grounded. figure 6-10. typical irq multiplexing 74x153 1c0 1y 1g irq[0] irq_mux[0] 1c1 1c2 1c3 2c0 2c1 2c2 2c3 a b 2g 2y irq_mux[1] irq[1] irq[2] irq[3] irq[4] irq[5] irq[6] irq[7] 74x153 1c0 1y 1g irq_mux[2] 1c1 1c2 1c3 2c0 2c1 2c2 2c3 a b 2g 2y irq_mux[3] irq[8] irq[9] irq[10] irq[11] irq[12] irq[13] irq[14] irq[15] isa_clk2x isa_clk timer 0 keyboard slave pic com2/com4 com1/com3 lpt2 lpt1 rtc mouse fpu pci / ide pci / ide floppy floppy design guidelines 68/87 release 1.3 - january 29, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. the figure below describes a complete implementation of the external glue logic for dma request time-multiplexing and dma acknowledge demultiplexing. like for the interrupt lines, this logic can be simplified when only few dma channels are used in the application. this glue logic is not needed in local bus mode as it does not support dma transfers. figure 6-11. typical dma multiplexing and demultiplexing 74x153 1c0 1y 1g drq[0] dreq_mux[0] 1c1 1c2 1c3 2c0 2c1 2c2 2c3 a b 2g 2y dreq_mux[1] drq[1] drq[2] drq[3] drq[4] drq[5] drq[6] drq[7] 74x138 y0# a g2b dack0# y1# y2# y3# y4# y5# y6# y7# c b g2a isa_clk2x isa_clk isa, refresh isa, pio isa, fdc isa, pio slave dmac isa isa isa g1 dma_enc[0] dma_enc[1] dma_enc[2] dack1# dack2# dack3# dack5# dack6# dack7# design guidelines release 1.3 - january 29, 2002 69/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.3.7. ide / isa dynamic demultiplexing some of the isa bus signals are dynamically multiplexed to optimize the pin count. figure 6-12 describes how to implement the external glue logic to demultiplex the ide and isa interfaces. in local bus mode the two buffers are not needed and the nand gates can be simplified to inverters. 6.3.8. basic audio using ide interface when the application requires only basic audio capabilities, an audio dac on the ide interface can avoid using a pci-based audio device. this low cost solution is not cpu consuming thanks to the dma controller implemented in the ide controller and can generate 16-bit stereo sound. the clock speed is programmable when using the speaker output. figure 6-12. typical ide / isa demultiplexing master# 74xx245 rmrtccs# a b dir oe isaoe# kbcs# rtcrw# rtcds sa[19:8] stpc bus / dd[15:0] la[24] la[25] la[22] la[23] scs1# scs3# pcs1# pcs3# figure 6-13. basic audio on ide 74xx74 16 q q dd[15:0] d pr rst d[15:0] cs# pcs1 wr# a/b audio out right left stereo dac pdrq sysrsto# speaker pdiow# vcc vcc vcc stpc q q d pr rst note * : the inverter can be removed when the dac cs# is directly connected to gnd * design guidelines 70/87 release 1.3 - january 29, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.3.9. jtag interface the stpc integrates a jtag interface for scan- chain and on-board testing. the only external device needed are the pull up resistors. figure 6- 14 describes a typical implementation using these devices. fi g ure 6-14. typical jtag implementation stpc tclk tdo 3v3 connector 9 10 1 2 6 7 3 4 8 5 tms tdi trst 3v3 3v3 3v3 design guidelines release 1.3 - january 29, 2002 71/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.4. place and route recommendations 6.4.1. general recommendations some stpc interfaces run at high speed and need to be carefully routed or even shielded like: 1) memory interface 2) pci bus 3) 14 mhz oscillator stage all clock signals have to be routed first and shielded for speeds of 27mhz or higher. the high speed signals follow the same constraints, as for the memory and pci control signals. the next interfaces to be routed are memory and pci. all the analog noise-sensitive signals have to be routed in a separate area and hence can be routed indepedently. figure 6-15. shielding signals ground ring ground pad shielded signal line ground pad shielded signal lines design guidelines 72/87 release 1.3 - january 29, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.4.2. memory interface 6.4.2.1. introduction in order to achieve sdram memory interfaces which work at clock frequencies of 100 mhz and above, careful consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken into consideration. the guidelines described below are related to sdram components on dimm modules. for applications where the memories are directly soldered to the motherboard, the pcb should be laid out such that the trace lengths fit within the constraints shown here. the traces could be slightly shorter since the extra routing on the dimm pcb is no longer present but it is then up to the user to verify the timings. 6.4.2.2. sdram clocking scheme the sdram clocking scheme deserves a special mention here. basically the memory clock is generated on-chip through a pll and goes directly to the mclko output pin of the stpc. the nominal frequency is 100 mhz. because of the high load presented to the mclk on the board by the dimms it is recommended to rebuffer the mclko signal on the board and balance the skew to the clock ports of the different dimms and the mclki input pin of stpc. 6.4.2.3. board layout issues the physical layout of the motherboard pcb assumed in this presentation is as shown in figure 6-17 . because all of the memory interface signal balls are located in the same region of the stpc device, it is possible to orientate the device to reduce the trace lengths. the worst case routing length to the dimm1 is estimated to be 100 mm. solid power and ground planes are a must in order to provide good return paths for the signals and to reduce emi and noise. also there should be ample high frequency decoupling between the power and ground planes to provide a low impedance path between the planes for the return paths for signal routings which change layers. if possible, the traces should be routed adjacent to the same power or ground plane for the length of the trace. for the sdram interface, the most critical signal is the clock. any skew between the clocks at the sdram components and the memory controller will impact the timing budget. in order to get well matched clocks at all components it is recommended that all the dimm clock pins, stpc figure 6-16. clock scheme dimm1 mclki mclko dimm2 pll register pll ma[ ] + control md[63:0] sdram controller design guidelines release 1.3 - january 29, 2002 73/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. memory clock input (mclki) and any other component using the memory clock are individually driven from a low skew clock driver with matched routing lengths. in other words, all clock line lengths that go from the buffer to the memory chips (mclkx) and from the buffer to the stpc (mclki) must be identical. this is shown in figure 6-18 . the maximum skew between pins for this part is 250ps. the important factors for the clock buffer are a consistent drive strength and low skew between the outputs. the delay through the buffer is not important so it does not have to be a zero delay pll type buffer. the trace lengths from the clock driver to the dimm ckn pins should be matched exactly. since the propagation speed can vary between pcb layers, the clocks should be routed in a consistent way. the routing to the stpc memory input should be longer by 75 mm to compensate for the extra clock routing on the dimm. also a 20 pf capacitor should be placed as near as possible to the clock input of the stpc to compensate for the dimms higher clock load. the impedance of the trace used for the clock routing should be matched to the dimm clock trace impedance (60-75 ohms) . to minimise crosstalk the clocks should be routed with spacing to adjacent tracks of at least twice the clock trace width. for designs which use sdrams directly mounted on the motherboard pcb all the clock trace lengths should be matched exactly. figure 6-17. dimm placement dimm2 dimm1 stpc 35mm 35mm 15mm 10mm 116mm sdram i/f figure 6-18. clock routing mclko dimm ckn input stpc mclki dimm ckn input dimm ckn input low skew clock driver: l l+75mm* 20pf * no additional 75mm when sdram directly soldered on board design guidelines 74/87 release 1.3 - january 29, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. the dimm sockets should be populated starting with the furthest dimm from the stpc device first (dimm1). there are two types of dimm devices; single-row and dual-row. the dual-row devices require two chip select signals to select between the two rows. a stpc device with 4 chip select control lines could control either 4 single-row dimms or 2 dual-row dimms. when only 2 chip select control lines are activated, only two single- row dimms or one dual-row dimm can be controlled. when using dimm modules, schematics have to be done carefully in order to avoid data buses completely crossing on the board. this has to be checked at the library level. in order to achieve the layout shown in figure 6-19 , schematics have to implement the crossing described in figure 6-20 . the dqm signals must be exchanged using the same order. 6.4.2.4. summary for unbuffered dimms the address/control signals will be the most critical for timing. the simulations show that for these signals the best way to drive them is to use a parallel termination. for applications where speed is not so critical series termination can be used as this will save power. using a low impedance such as 50 w for these critical traces is recommended as it both reduces the delay and the overshoot. the other memory interface signals will typically be not as critical as the address/control signals. using lower impedance traces is also beneficial for the other signals but if their timing is not as critical as the address/control signals they could use the default value. using a lower impedance implies using wider traces which may have an impact on the routing of the board. the layout of this interface can be validated by an electrical simulation using the ibis model available on the stpc web site. figure 6-19. optimum data bus layout for dimm figure 6-20. schematics for optimum data bus layout for dimm dimm stpc sdram i/f d[15:00] d[31:16] d[47:32] d[63:48] md[31:00] md[63:32] md[15:00],dqm[1:0] md[31:16],dqm[3:2] md[47:32],dqm[5:4] md[63:48],dqm[7:6] d[15:00],dqm[1:0] d[31:16],dqm[3:2] d[47:32],dqm[5:4] d[63:48],dqm[7:6] dimm stpc design guidelines release 1.3 - january 29, 2002 75/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.4.3. pci interface 6.4.3.1. introduction in order to achieve a pci interface which work at clock frequencies up to 33mhz, careful consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken into consideration. 6.4.3.2. pci clocking scheme the pci clocking scheme deserves a special mention here. basically the pci clock (pciclko) is generated on-chip from hclk through a programmable delay line and a clock divider. the nominal frequency is 33mhz. this clock must be looped to pciclki and goes to the internal south bridge through a deskewer. on the contrary, the internal north bridge is clocked by hclk, putting some additionnal constraints on t 0 and t 1 . figure 6-21. clock scheme hclk pll 1/2 1/3 1/4 clock strap options pciclko t 1 pciclki hclk ad[31:0] south north deskewer mux t 0 t 2 delay stpc md[30:27] md[17,4] md[7:6] bridge bridge design guidelines 76/87 release 1.3 - january 29, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.4.3.3. board layout issues the physical layout of the motherboard pcb assumed in this presentation is as shown in figure 6-22 . for the pci interface, the most critical signal is the clock. any skew between the clocks at the pci components and the stpc will impact the timing budget. in order to get well matched clocks at all components it is recommended that all the pci clocks are individually driven from a serial resistance with matched routing lengths. in other words, all clock line lengths that go from the resistor to the pci chips (pciclkx) must be identical. the figure below is for pci devices soldered on- board. in the case of a pci slot, the wire length must be shortened by 2.5" to compensate the clock layout on the pci board. the maximum clock skew between all devices is 2ns according to pci specifications. the figure 6-23 describes a typical clock delay implementation. the exact timing constraints are listed in the pci section of the electrical specifications chapter. figure 6-22. typical pci clock routing length(pciclki) = length(pciclkx) with x = {a,b,c} note : the value of 22 ohms corresponds to tracks with z 0 = 70 ohms. pciclki pciclko pciclka pciclkb pciclkc device a device b device c figure 6-23. clocks relationships pciclko pciclki hclk pciclkx design guidelines release 1.3 - january 29, 2002 77/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.4.4. thermal dissipation 6.4.4.1. power saving thermal dissipation of the stpc depends mainly on supply voltage. when the system does not need to work at the upper voltage limit, it may therefore be beneficial to reduce the voltage to the lower voltage limit, where possible. this could save a few 100s of mw. the second area to look at is unused interfaces and functions. depending on the application, some input signals can be grounded, and some blocks not powered or shutdown. clock speed dynamic adjustment is also a solution that can be used along with the integrated power management unit. 6.4.4.2. thermal balls the standard way to route thermal balls to ground layer implements only one via pad for each ball pad, connected using a 8-mil wire. with such configuration the plastic bga package does 90% of the thermal dissipation through the ground balls, and especially the central thermal balls which are directly connected to the die. the remaining 10% is dissipated through the case. adding a heat sink reduces this value to 85%. as a result, some basic rules must be followed when routing the stpc in order to avoid thermal problems. as the whole ground layer acts as a heat sink, the ground balls must be directly connected to it, as illustrated in figure 6-24 . if one ground layer is not enough, a second ground plane may be added. when possible, it is important to avoid other devices on-board using the pcb for heat dissipation, like linear regulators, as this would heat the stpc itself and reduce the temperature range of the whole system, in case these devices can not use a separate heat sink, they must not be located just near the stpc figure 6-24. ground routing pad for ground ball thru hole to ground layer t o p l a y e r : s i g n a l s p o w e r l a y e r i n t e r n a l l a y e r : s i g n a l s b o t t o m l a y e r : g r o u n d l a y e r note: for better visibility, ground balls are not all routed. design guidelines 78/87 release 1.3 - january 29, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. when considering thermal dissipation, one of the most important parts of the layout is the connection between the ground balls and the ground layer. a 1-wire connection is shown in figure 6-25 . the use of a 8-mil wire results in a thermal resistance of 105c/w assuming copper is used (418 w/ m.k). this high value is due to the thickness (34 m) of the copper on the external side of the pcb. considering only the central matrix of 36 thermal balls and one via for each ball, the global thermal resistance is 2.9c/w. this can be easily improved using four 12.5 mil wires to connect to the four vias around the ground pad link as in figure 6-26 . this gives a total of 49 vias and a global resistance for the 36 thermal balls of 0.5c/ w. the use of a ground plane like in figure 6-27 is even better. figure 6-25. recommended 1-wire power/ground pad layout solder mask (4 mil) pad for ground ball (diameter = 25 mil) hole to ground layer (diameter = 12 mil) connection wire (width = 12.5 mil) via (diameter = 24 mil) 34.5 mil 1 mil = 0.0254 mm figure 6-26. recommended 4-wire ground pad layout 4 via pads for each ground ball design guidelines release 1.3 - january 29, 2002 79/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. to avoid solder wicking over to the via pads during soldering, it is important to have a solder mask of 4 mil around the pad (nsmd pad). this gives a diameter of 33 mil for a 25 mil ground pad. to obtain the optimum ground layout, place the vias directly under the ball pads. in this case no local board distortion is tolerated. 6.4.4.3. heat dissipation the thickness of the copper on pcb layers is typically 34 m for external layers and 17 m for internal layers. this means that thermal dissipation is not good; high board temperatures are concentrated around the devices and these fall quickly with increased distance. where possible, place a metal layer inside the pcb; this improves dramatically the spread of heat and hence the thermal dissipation of the board. the possibility of using the whole system box for thermal dissipation is very useful in cases of high internal temperatures and low outside temperatures. bottom side of the pbga should be thermally connected to the metal chassis in order to propagate the heat flow through the metal. thermally connecting also the top side will improve furthermore the heat dissipation. figure 6-28 illustrates such an implementation. figure 6-27. optimum layout for central ground ball - top layer via to ground layer pad for ground ball clearance = 6mil diameter = 25 mil hole diameter = 14 mil solder mask diameter = 33 mil external diameter = 37 mil connections = 10 mil figure 6-28. use of metal plate for thermal dissipation metal planes thermal conductor board die design guidelines 80/87 release 1.3 - january 29, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. as the pcb acts as a heat sink, the layout of top and ground layers must be done with care to maximize the board surface dissipating the heat. the only limitation is the risk of losing routing channels. figure 6-29 and figure 6-30 show a routing with a good thermal dissipation thanks to an optimized placement of power and signal vias. the ground plane should be on bottom layer for the best heat spreading (thicker layer than internal ones) and dissipation (direct contact with air). . figure 6-29. layout for good thermal dissipation - top layer 1 a 3.3v ball 2.5v ball (core / plls) via stpc ball gnd ball not connected ball design guidelines release 1.3 - january 29, 2002 81/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. figure 6-30. recommend signal wiring (top & ground layers) with corresponding heat flow stpc balls external row internal row gnd power power design guidelines 82/87 release 1.3 - january 29, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6.5. debug methodology in order to bring a stpc-based board to life with the best efficiency, it is recommended to follow the check-list described in this section. 6.5.1. power supplies in parallel with the assembly process, it is useful to get a bare pcb to check the potential short- circuits between the various power and ground planes. this test is also recommended when the first boards are back from assembly. this will avoid bad surprises in case of a short-circuit due to a bad soldering. when the system is powered, all power supplies, including the pll power pins must be checked to be sure the right level is present. see table 4-2 for the exact supported voltage range: vdd_core: 2.5v vdd_xxxpll: 2.5v vdd: 3.3v 6.5.2. boot sequence 6.5.2.1. reset input the checking of the reset sequence is the next step. the waveform of sysrsti# must complies with the timings described in figure 4-3 . this signal must not have glitches and must stay low until the 14.31818mhz output (osc14m) is at the right frequency and the strap options are stabilized to a valid configuration. in case this clock is not present, check the 14mhz oscillator stage (see figure 6-3 ). 6.5.2.2. strap options the stpc has been designed in a way to allow configurations for test purpose that differs from the functional configuration. in many cases, the troubleshootings at this stage of the debug are the resulting of bad strap options. this is why it is mandatory to check they are properly setup and sampled during the boot sequence. the list of all the strap options is summarized at the beginning of section 3. 6.5.2.3. clocks once osc14m is checked and correct, the next signals to measure are the host clock (hclk), pci clocks (pci_clko, pci_clki) and memory clock (mclko, mclki). hclk must run at the speed defined by the corresponding strap options (see table 3-1) and must not be more than 100mhz. in x2 cpu clock mode, this clock must be limited to 66mhz. pci_clki and pci_clko must be connected as described in figure 6-19 and not be higher than 33mhz. their speed depends on hclk and on the divider ratio defined by the md[4] and md[17] strap options as described in section 3. to ensure a correct behaviour of the device, the pci deskewing logic must be configured properly by the md[7:6] strap options according to section 3. for timings constraints, refers to section 4. mclki and mclko must be connected as described in figure 6-3 to figure 6-5 depending on the sdram implementation. the memory clock must run at hclk speed when in synchronous mode and must not be higher than 100mhz in any case. 6.5.2.4. reset output if sysrsti# and all clocks are correct, then the sysrsto# output signal should behave as described in figure 4-3 . 6.5.3. isa mode prior to check the isa bus control signals, pci_clki, isa_clk, isa_clk2x, and dev_clk must be running properly. if it is not the case, it is probably because one of the previous steps has not been completed. 6.5.3.1. first code fetches when booting on the isa bus, the two key signals to check at the very beginning are rmrtccs# and frame#. the first one is a chip select for the boot flash and is multiplexed with the ide interface. it should toggle together with isaoe# and memrd# to fetch the first 16 bytes of code. this corresponds to the loading of the first line of the cpu cache. in case rmrtccs# does not toggle, it is then necessary to check the pci frame# signal. indeed the isa controller is part of the south bridge and all isa bus cycles are visible on the pci bus. if there is no activity on the pci bus, then one of the previous steps has not been checked properly. if there is activity then there must be something conflicting on the isa bus or on the pci bus. 6.5.3.2. boot flash size the isa bus supports 8-bit and 16-bit memory devices. in case of a 16-bit boot flash, the signal memcs16# must be activated during design guidelines release 1.3 - january 29, 2002 83/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. rmrtccs# cycle to inform the isa controller of a 16-bit device. 6.5.3.3. post code once the 16 first bytes are fetched and decoded, the cpu core continue its execution depending on the content of these first data. usually, it corresponds to a jump instruction and the code fetching continues, generating read cycles on the isa bus. most of the bios and boot loaders are reading the content of the flash, decompressing it in sdram, and then continue the execution by jumping to the entry point in ram. this boot process ends with a jump to the entry point of the os launcher. these various steps of the booting sequence are codified by the so-called post codes (power-on self-test). a 8-bit code is written to the port 80h at the beginning of each stage of the booting process (i/o write to address 0080h) and can be displayed on two 7-segment display, enabling a fast visual check of the booting completion level. usually, the last post code is 0x00 and corresponds to the jump into the os launcher. when the execution fails or hangs, the lastest written code stays visible on that display, indicating either the piece of code to analyse, either the area of the hardware not working properly. 6.5.4. local bus mode as the local bus controller is located into the host interface, there is no access to the cycles on the pci, reducing the amount of signals to check. 6.5.4.1. first code fetches when booting on the local bus, the key signal to check at the very beginning is fcs0#. this signal is a chip select for the boot flash and should toggle together with prd# to fetch the first 16 bytes of code. this corresponds to the loading of the first line of the cpu cache. in case fcs0# does not toggle, then one of the previous steps has not been done properly, like hclk speed and cpu clock multiplier (x1, x2). 6.5.4.2. boot flash size the local bus support 16-bit boot memory devices only. 6.5.4.3. post code like in isa mode, post codes can be implemented on the local bus. the difference is that an iocs# must be programmed at i/o address 80h prior to writing these code, the post display being connected to this iocs# and to the lower 8 bits of the bus. 6.5.5. summary here is a check-list for the stpc board debug from power-on to cpu execution. for each step, in case of failure, verify first the corresponding balls of the stpc: - check if the voltage or activity is correct - search for potential shortcuts. for troubleshooting in steps 5 to 10, verify the related strap options: - value & connection. refer to section 3. - see figure 4-3 for timing constraints steps 8a and 9a are for debug in isa mode while steps 8b and 9b are for local bus mode. check: how? troubleshooting 1 power supplies verify that voltage is within specs: - this must include hf & lf noise - avoid full range sweep refer to table 4-1 for values measure voltage near stpc balls: - use very low gnd connection. add some decoupling capacitor: - the smallest, the nearest to stpc balls. 2 14.318 mhz verify osc14m speed the 2 capacitors used with the quartz must match with the capacitance of the crystal. try other values. 3 sysrsti# (power good) measure sysrsti# of stpc see figure 4-3 for waveforms. verify reset generation circuit: - device reference - components value 5 hclk measure hclk is at selected frequency 25mhz < hclk < 100mhz hclk wire must be as short as possible design guidelines 84/87 release 1.3 - january 29, 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 6 pci clocks measure pciclko: - maximum is 33mhz by standard - check it is at selected frequency - it is generated from hclk by a division (1/2, 1/3 or 1/4) check pciclki equals pciclko verify pciclko loops to pciclki. verify maximum skew between any pci clock branch is below 2ns. in synchronous mode, check mclki. 7 memory clocks measure mclko: - use a low-capacitance probe - maximum is 100mhz - check it is at selected frequency - in sync mode mclk=hclk - in async mode, default is 66mhz check mclki equals mclko verify load on mclki. verify mclk programming (bios setting). 4 sysrsto# measure sysrsto# of stpc see figure 4-3 for waveforms. verify sysrsti# duration. verify sysrsti# has no glitch verify clocks are running. 8a pci cycles check pci signals are toggling: - frame#, irdy#, trdy#, devsel# - these signals are active low. check, with a logic analyzer, that first pci cycles are the expected ones: memory read starting at address with lower bits to 0xfff0 verify pci slots if the stpc dont boot - verify data read from boot memory is ok - ensure flash is correctly programmed - ensure cmos is cleared. 9a isa cycles to boot memory check rmrtccs# & memrd# check directly on boot memory pin verify memcs16#: - must not be asserted for 8-bit memory verify iochrdy is not be asserted verify isaoe# pin: - it controls ide / isa bus demultiplexing 8b local bus cycles to boot memory check fcs0# & prd# check directly on boot memory pin verify hclk speed and cpu clock mode. 9b check, with a logic analyzer, that first local bus cycles are the expected one: memory read starting at the top of boot memory less 16 bytes if the stpc dont boot - verify data read from boot memory is ok - ensure flash is correctly programmed - ensure cmos is cleared. 10 the cpu fills its first cache line by fetching 16 bytes from boot memory. then, first instructions are executed from the cpu. any boot memory access done after the first 16 bytes are due to the instructions executed by the cpu => minimum hardware is correctly set, cpu executes code. please have a look to the bios writers guide or programming manual to go further with your board testing. check: how? troubleshooting ordering data release 1.3 - january 29, 2002 85/87 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 7. ordering data 7.1. ordering codes st pc e1 e e b c stmicroelectronics prefix product family pc: pc compatible product id e1: ELITE core speed e: 100 mhz h: 133 mhz memory interface speed e: 100 mhz d: 90 mhz package b: 388 overmoulded bga temperature range c: commercial case temperature (tcase) = 0c to +85c i: industrial case temperature (tcase) = -40c to +115c ordering data 86/87 release 1.3 - januar y 29, 2002 this is preliminary information on a new product now in development or under g oin g evaluation. details are subject to chan g e without notice. 7.2. available part numbers 7.3. customer service more information is available on the stmicroelectronics internet site http:// www.st.com/stpc part number core frequency ( mhz ) cpu mode ( x1 / x2 ) memory interface speed (mhz) tcase range ( c ) stpce1eebc 100 x1 100 0c to +85 stpce1hdbc 133 x2 90 stpce1eebi 100 x1 100 -40c to +115 stpce1hdbi 133 x2 90 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 2000 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 87 release 1.3 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. |
Price & Availability of ELITE
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |